Quartus® Prime Design Software v18.0

By Intel® FPGAs 157

Quartus® Prime Design Software v18.0

Intel Quartus Prime software v18.0 has improvements made across the three key areas that designers care about the most—performance, productivity, and usability. Intel Quartus Prime Pro Edition software v18.0 supports Intel Stratix® 10 TX, MX, SX, and GX devices. Accelerate FPGA development with faster compile times of Intel Stratix 10 designs in v18.0 as compared to prior releases. Larger Intel Stratix 10 designs show greater compile time reduction. There are additional settings on how to reduce compile time that can be accessed in the compiler user guide. With Intel Quartus prime pro edition software v18.0, designs will now experience a significant reduction in peak virtual memory requirements as compared to the 17.1.1 release. All Intel Stratix 10 designs compile in less than 64 GB of memory space.

Concurrent analysis support provides the ability to analyze the results of a design while compilation is running. This feature is supported with timing analyzer, netlist viewers, and compilation reports, enabling designs to be completed much faster. Partial reconfiguration (PR) allows users to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function. With Intel Quartus Prime Pro Edition software v18.0, users can accelerate their applications using Intel FPGA programming tools on the Cloud to program FPGAs in a high-performance computing environment provided by Nimbix. Learn more on the Cloud services web page.

Learn and understand more with the links provided in the resources section below.

Features
  • Faster compile time
  • Reduction in peak virtual memory
  • Concurrent analysis
  • PR allows users to configure a portion of the FPGA dynamically
  • Software tools on the Cloud
  • Allow coherency signals from Intel Stratix 10 device hard processor system (HPS) interface to be transported to intellectual property (IP) via ACE-lite support
  • Incorporate IOP components that use SystemVerilog interfaces into platform designer systems
  • Experience a significant reduction in IP upgrade regeneration time
Applications
  • Platform designer can generate hierarchical simulation scripts by referencing simulation information of its subsystems and IP components without traversing system hierarchy
  • High-resolution display support provides an updated GUI to support new platforms and scalable icons for high-resolution displays
  • Interface planner can be launched without having to close the Intel Quartus software GUI in improved tool integration
  • See the Intel Quartus prime software support page for additional applications
  • Use Verilog syntax to connect ports in platform designer with wire-level connectivity
Resources
  • Compiler user guide
  • Concurrent analysis
  • Cloud services web page
  • Hierarchical simulation scripts
  • Wire-level connectivity
  • Improved tool integration
  • Intel Quartus prime software support
  • What's new in Intel Quartus prime software v18.0 training
  • AN 307: Intel FPGA design flow for Xilinx users

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