SN74LVT8996PW

Mfr. #:: SN74LVT8996PW
Description:: Specialty Function Logic 3.3V 10-Bit Add Port Multi-Add Tap Trncvr
Lifecycle:: New from this manufacturer.
Datasheet:: SN74LVT8996PW Datasheet
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More Information:: SN74LVT8996PW more Information SN74LVT8996PW Product Details

Product Attribute
Attribute Value

Manufacturer:: Texas Instruments

Product Category:: Specialty Function Logic

RoHS:: Y

Product:: Boundry Scan JTAG Logic

Series:: SN74LVT8996

Operating Supply Voltage:: 2.7 V to 3.6 V

Minimum Operating Temperature:: - 40 C

Maximum Operating Temperature:: + 85 C

Package / Case:: TSSOP-24

Packaging:: Tube

Operating Temperature Range:: - 40 C to + 85 C

Brand:: Texas Instruments

Mounting Style:: SMD/SMT

Product Type:: Specialty Function Logic

Factory Pack Quantity:: 60

Subcategory:: Logic ICs

Unit Weight:: 0.003157 oz

Tags: SN74LVT8996P, SN74LVT899, SN74LVT8, SN74LVT, SN74LV, SN74L, SN74, SN7

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SN74LVT8996PW Description

***ow.cn: Addressable Scan Port -40°C to 85°C 24-Pin TSSOP Tube

***as Instruments: 3.3-V ABT 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) TAP Transceiver 24-TSSOP -40 to 85

***nell: SCAN PORT/TAP TRANSCEIVER, 10BIT, TSSOP

***i-Key: IC 10-BIT SCAN PORT XCVR 24TSSOP

***et: 3.3V ABT 10-BIT ADDRESS SCAN PORTS

***i-Key Marketplace: SN74LVT8996 3.3-V ABT 10-BIT ADD

***INS: The 'LVT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most SCOPETM devices, the ASP is not a boundary-scannable device, rather, it applies TI's addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level.

***AS INST: These devices are functionally equivalent to the 'ABT8996 ASPs. Additionally, they are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to interface to 5-V masters and/or targets.

***: Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP signals to a set of secondary TAP signals - for example, to interface backplane TAP signals to a board-level TAP. The ASP provides all signal buffering that might be required at these two interfaces. When primary and secondary TAPs are connected, only a moderate propagation delay is introduced - no storage/retiming elements are inserted. This minimizes the need for reformatting board-level test vectors for in-system use.

***AS INSTRUMENTS INCORPORATED: Most operations of the ASP are synchronous to the primary test clock (PTCK) input. PTCK is always buffered directly onto the secondary test clock (STCK) output.

***ASI: Upon power up of the device, the ASP assumes a condition in which the primary TAP is disconnected from the secondary TAP (unless the bypass signal is used, as below). This reset condition also can be entered by the assertion of the primary test reset (PTRST\) input or by use of shadow protocol. PTRST\ is always buffered directly onto the secondary test reset (STRST\) output, ensuring that the ASP and its associated secondary TAP can be reset simultaneously.

***ASI: When connected, the primary test data input (PTDI) and primary test mode select (PTMS) input are buffered onto the secondary test data output (STDO) and secondary test mode select (STMS) output, respectively, while the secondary test data input (STDI) is buffered onto the primary test data output (PTDO). When disconnected, STDO is at high impedance, while PTDO is at high impedance, except during acknowledgment of a shadow protocol. Upon disconnect of the secondary TAP, STMS holds its last low or high level, allowing the secondary TAP to be held in its last stable state. Upon reset of the ASP, STMS is high, allowing the secondary TAP to be synchronously reset to the Test-Logic-Reset state.

***AS INSTRUMENTS INC: In system, primary-to-secondary connection is based on shadow protocols that are received and acknowledged on PTDI and PTDO, respectively. These protocols can occur in any of the stable TAP states other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset, Run-Test/Idle, Pause-DR or Pause-IR). The essential nature of the protocols is to receive/transmit an address via a serial bit-pair signaling scheme. When an address is received serially at PTDI that matches that at the parallel address inputs (A9-A0), the ASP serially retransmits its address at PTDO as an acknowledgment and then assumes the connected (ON) status, as above. If the received address does not match that at the address inputs, the ASP immediately assumes the disconnected (OFF) status without acknowledgment.

***AS: The ASP also supports three dedicated addresses that can be received globally (that is, to which all ASPs respond) during shadow protocols. Receipt of the dedicated disconnect address (DSA) causes the ASP to disconnect in the same fashion as a nonmatching address. Reservation of this address for global use ensures that at least one address is available to disconnect all receiving ASPs. The DSA is especially useful when the secondary TAPs of multiple ASPs are to be left in different stable states. Receipt of the reset address (RSA) causes the ASP to assume the reset condition, as above. Receipt of the test-synchronization address (TSA) causes the ASP to assume a connect status (MULTICAST) in which PTDO is at high impedance but the connections from PTMS to STMS and PTDI to STDO are maintained to allow simultaneous operation of the secondary TAPs of multiple ASPs. This is useful for multicast TAP-state movement, simultaneous test operation (such as in Run-Test/Idle state), and scanning of common test data into multiple like scan chains. The TSA is valid only when received in the Pause-DR or Pause-IR TAP states.

***AS INSRUMENT: Alternatively, primary-to-secondary connection can be selected by assertion of a low level at the bypass (BYP\) input. This operation is asynchronous to PTCK and is independent of PTRST\ and/or power-up reset. This bypassing feature is especially useful in the board-test environment, since it allows the board-level automated test equipment (ATE) to treat the ASP as a simple transceiver. When the BYP\ input is high, the ASP is free to respond to shadow protocols. Otherwise, when BYP\ is low, shadow protocols are ignored.

***AS INS: Whether the connected status is achieved by use of shadow protocol or by use of BYP\, this status is indicated by a low level at the connect (CON\) output. Likewise, when the secondary TAP is disconnected from the primary TAP, the CON\ output is high.

***TEXAS: The SN54LVT8996 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT8996 is characterized for operation from -40°C to 85°C.

Market price

Part #	Description	Stock	Price
SN74LVT8996PW DISTI # V39:1801_07360072	Addressable Scan Port 24-Pin TSSOP Tube RoHS: Compliant	15	9000:$7.5960 6000:$7.6690 3000:$7.7430 60:$10.1840
SN74LVT8996PWR DISTI # 296-8657-1-ND	IC 10-BIT SCAN PORT XCVR 24TSSOP RoHS: Compliant Min Qty: 1 Container: Cut Tape (CT)	1215In Stock	1000:$7.1481 500:$7.7931 100:$8.7605 10:$10.3730 1:$11.2900
SN74LVT8996PWR DISTI # 296-8657-6-ND	IC 10-BIT SCAN PORT XCVR 24TSSOP RoHS: Compliant Min Qty: 1 Container: Digi-Reel®	1215In Stock	1000:$7.1481 500:$7.7931 100:$8.7605 10:$10.3730 1:$11.2900
SN74LVT8996PW DISTI # 296-8657-5-ND	IC 10-BIT SCAN PORT XCVR 24TSSOP RoHS: Compliant Min Qty: 1 Container: Tube	121In Stock	1020:$8.2633 540:$9.0089 120:$10.1272 60:$11.4940 10:$11.9910 1:$13.0500
SN74LVT8996PWR DISTI # 296-8657-2-ND	IC 10-BIT SCAN PORT XCVR 24TSSOP RoHS: Compliant Min Qty: 2000 Container: Tape & Reel (TR)	Temporarily Out of Stock	2000:$6.6790
SN74LVT8996PWR DISTI # 29457419	Addressable Scan Port 24-Pin TSSOP T/R RoHS: Compliant	8000	4000:$6.6046 2000:$6.7410
SN74LVT8996PW DISTI # 29458819	Addressable Scan Port 24-Pin TSSOP Tube RoHS: Compliant	4080	4500:$8.0673 3000:$8.3900 1500:$8.8627 60:$9.3918
SN74LVT8996PW DISTI # 25731107	Addressable Scan Port 24-Pin TSSOP Tube RoHS: Compliant	15	15:$10.1840
SN74LVT8996PW DISTI # SN74LVT8996PW	Addressable Scan Port 24-Pin TSSOP Tube (Alt: SN74LVT8996PW) RoHS: Compliant Min Qty: 1 Container: Tube	Europe - 15	1:€12.0000 10:€10.4300 25:€9.8800 50:€9.3500 100:€8.8100 250:€7.2100
SN74LVT8996PWR DISTI # SN74LVT8996PWR	Addressable Scan Port 24-Pin TSSOP T/R - Tape and Reel (Alt: SN74LVT8996PWR) RoHS: Compliant Min Qty: 2000 Container: Reel	Americas - 2000	2000:$7.4900 4000:$7.1900 8000:$6.8900 12000:$6.6900 20000:$6.4900
SN74LVT8996PW DISTI # SN74LVT8996PW	Addressable Scan Port 24-Pin TSSOP Tube - Rail/Tube (Alt: SN74LVT8996PW) RoHS: Compliant Min Qty: 60 Container: Tube	Americas - 0	60:$8.9900 120:$8.4900 240:$8.1900 360:$7.9900 600:$7.6900
SN74LVT8996PWR DISTI # SN74LVT8996PWR	Addressable Scan Port 24-Pin TSSOP T/R (Alt: SN74LVT8996PWR) RoHS: Compliant Min Qty: 2000 Container: Tape and Reel	Asia - 0
SN74LVT8996PWR DISTI # SN74LVT8996PWR	Addressable Scan Port 24-Pin TSSOP T/R (Alt: SN74LVT8996PWR) RoHS: Compliant Min Qty: 2000 Container: Tape and Reel	Europe - 0	2000:€8.7900 4000:€7.6900 8000:€6.8900 12000:€6.5900 20000:€6.2900
SN74LVT8996PW DISTI # 68Y8047	SCAN PORT/TAP TRANSCEIVER, 10BIT, TSSOP,Logic Type:JTAG Addressable Scan Port,Logic Case Style:TSSOP,No. of Pins:24Pins,Supply Voltage Min:2.7V,Supply Voltage Max:3.6V,Operating Temperature Min:-40°C,Operating Temperature RoHS Compliant: Yes	0
SN74LVT8996PW	3.3-V ABT 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) TAP Transceiver	120	1000:$7.0600 750:$7.2100 500:$8.3300 250:$9.5700 100:$10.2500 25:$11.4300 10:$12.2400 1:$13.6100
SN74LVT8996PWR	3.3-V ABT 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) TAP Transceiver	2000	1000:$5.9300 750:$6.0500 500:$6.9900 250:$8.0400 100:$8.6100 25:$9.6000 10:$10.2800 1:$11.4300
SN74LVT8996PW	Microprocessor Circuit, BICMOS, PDSO24 RoHS: Compliant	26	1000:$8.1700 500:$8.6000 100:$8.9600 25:$9.3400 1:$10.0600
SN74LVT8996PWR	Microprocessor Circuit, BICMOS, PDSO24 RoHS: Compliant	1230	1000:$6.8700 500:$7.2300 100:$7.5300 25:$7.8500 1:$8.4500
SN74LVT8996PWR DISTI # 595-SN74LVT8996PWR	Specialty Function Logic 3.3V 10-Bit Add Port Multi-Add Tap Trncvr RoHS: Compliant	984	1:$10.9600 10:$10.0700 25:$9.5500 100:$8.5100 250:$8.0900 500:$7.5700 1000:$6.9400
SN74LVT8996PW DISTI # 595-SN74LVT8996PW	Specialty Function Logic 3.3V 10-Bit Add Port Multi-Add Tap Trncvr RoHS: Compliant	104	1:$13.0400 10:$11.9900 25:$11.3700 100:$10.1300 250:$9.6400 500:$9.0100
SN74LVT8996PW DISTI # 2499834	SCAN PORT/TAP TRANSCEIVER, 10BIT, TSSOP RoHS: Compliant	0	1:$20.6400 10:$18.9800 25:$17.9900 100:$16.0400 250:$15.2600 500:$14.2600 1000:$13.0900

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SN74LVT8996PW

Step1:Vacuum Packaging with PL

Step2:Anti-Static Bag

Step3:Packaging Boxes

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes