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SN74ALS569ADWG4

SN74ALS569ADWG4
Mfr. #:
SN74ALS569ADWG4
Description:
Counter ICs Synch 4B Up Down Binary Counters
Lifecycle:
New from this manufacturer.
Datasheet:
SN74ALS569ADWG4 Datasheet
Delivery:
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ECAD Model:
More Information:
SN74ALS569ADWG4 more Information SN74ALS569ADWG4 Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Counter ICs
RoHS:
Y
Mounting Style:
SMD/SMT
Package / Case:
SOIC-20
Counter Type:
Binary
Logic Family:
TTL
Number of Bits:
4
Counting Method:
Asynchronous
Counting Sequence:
Up/Down
Operating Supply Voltage:
4.5 V to 5.5 V
Packaging:
Tube
Brand:
Texas Instruments
Product Type:
Counter ICs
Factory Pack Quantity:
1
Subcategory:
Counter ICs
Unit Weight:
0.028254 oz
Tags
SN74ALS569AD, SN74ALS569A, SN74ALS569, SN74ALS56, SN74ALS5, SN74ALS, SN74AL, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC COUNTER BINARY 4BIT 20SOIC
***ser
Logic - Counters Synch 4B Up Down Binary Counters
***ark
Counter Logic IC; Logic Family:ALS; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; Package/Case:20-SOIC; No. of Pins:20; Operating Temperature Range:0°C to +70°C; Input Type:TTL; Leaded Process Compatible:Yes; Output Type:TTL ;RoHS Compliant: Yes
***as Instruments
The SN74ALS568A decade counter and ´ALS569A binary counters are programmable, count up or down, and offer both synchronous and asynchronous clearing. All synchronous functions are executed on the positive-going edge of the clock (CLK) input. The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). Asynchronous (direct) clearing overrides all other functions of the device, while synchronous clearing overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by holding load () low during a positive-going clock transition. The counting function is enabled only when enable P (ENP\) and enable T (ENT\) are low and ACLR\, SCLR\, and are high. The up/down (U/D\) input controls the direction of the count. These counters count up when U/D\ is high and count down when U/D\ is low. A high level at the output-enable () input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of . ENT\ is fed forward to enable the ripple-carry output (RCO\) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum (9 or 15) when counting up. The clocked carry output (CCO\) produces a low-level pulse for a duration equal to that of the low level of the clock when is low and the counter is enabled (both ENP\ and ENT\ are low); otherwise, CCO\ is high. CCO\ does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connecting or CCO\ of the first counter to ENT\ of the next counter. However, for very high-speed counting, should be used for cascading since CCO\ does not become active until the clock returns to the low level. The SN54ALS569A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS568A and SN74ALS569A are characterized for operation from 0°C to 70°C.
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