AD9144 Digital-to-Analog Converter

AD9144 Digital-to-Analog Converter

The AD9144 from Analog Devices features 82-dBc spurious-free dynamic range (SFDR) and a maximum sample rate of 2.8 GSPS permitting multicarrier generation up to the Nyquist frequency. With industry-leading -164 dBm/Hz noise spectral density, the AD9144 enables higher dynamic range transmitters to be built. Its advanced and proprietary low SFDR and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. A JESD204B eight-lane interface and low inherent latency of under two D/A converter clock cycles simplifies hardware and software system design while allowing for multichip synchronization.

The combination of programmable interpolation rate, high sample rates and low power at 1.5 W gives system designers flexibility when choosing D/A converter output frequencies. This is especially helpful in meeting four- to six-carrier GSM transmission specifications and other communications standards. For six carrier GSM IMD, the AD9144 operates at 77 dBc at 75-MHZ IF. Operating with the on-chip PLL (phase-locked loop) at a D/A converter output frequency of 30 MHz, the AD9144 delivers a 76-dB adjacent-channel leakage ratio (ACLR ) for four-carrier WCDMA applications. The AD9144 includes integrated interpolation filters with selectable interpolation factors of 2, 4, and 8. The dual D/A converter data interface supports word and byte load allowing customers to reduce input pins on lower data rates to save board space, power and cost. The AD9144 is supported by an evaluation board with an FPGA Mezzanine Card (FMC) connector, software, tools, SPI controller and reference designs. ADI’s VisualAnalog™ software package combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface allowing designers to customize their input signal and data analysis.

Features and Benefits
  • Supports input data rate >1 GSPS
  • Proprietary low spurious and distortion design
    • 6-carrier GSM IMD = 77 dBc at 75 MHz IF
    • SFDR = 82 dBc at DC IF, -9dBFS
    • Flexible 8-lane JESD204B interface Support dual DAC mode at 2.8 GSPS
  • Multiple chip synchronization
    • Fixed latency
    • Data generator latency compensation
  • Selectable 1×, 2×, 4×, 8× interpolation filter
    • Low power architecture
  • Input signal power detection
    • Emergency stop for downstream analog circuitry protection
  • Transmit enable function allows extra power saving
  • High performance, low noise PLL clock multiplier
  • Digital inverse sinc filter
  • Low power: 1.6 W at 1.6 GSPS, 1.7 W at 2.0 GSPS, full operating conditions
  • 88-lead LFCSP with exposed pad

Applications
  • Wireless communications
    • 3G/4G W-CDMA base stations
    • Wideband repeaters
    • Software defined radios
  • Wideband communications
    • Point-to-point
    • Local multipoint distribution service (LMDS) and multichannel multipoint distribution service (MMDS)
  • Transmit diversity, multiple input/multiple output (MIMO)
  • Instrumentation
  • Automated test equipment

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