3.3 V PCIe Clock Generator

By IDT, Integrated Device Technology Inc 60

3.3 V PCIe Clock Generator

IDT's 6- and 8-output 3.3 V clock generators operate at roughly one-fifth the power of traditional PCIe clock devices, effectively eliminating thermal concerns.

With their integrated terminations, the 9FGL06 and 9FGL08 devices’ ultra-compact 5 mm x 5 mm and 6 mm x 6 mm packages can deliver up to a 90 percent reduction in board area. Factory programmable versions provide quick turn device optimizations to meet exact customer requirements. The SoC-friendly devices greatly exceed the phase jitter requirements of the PCIe Gen3 specification in anticipation of the upcoming PCIe Gen4 specification, and are also suitable for applications needing less than 3 ps rms 12 k to 20 M phase jitter, such as gigabit Ethernet and other high-performance applications.

The 3.3 V devices are pin-compatible to IDT’s highly successful 1.5 V 9FGU-series and 1.8 V 9FGV-series PCIe clock generators. The timing family targets power- and space-constrained designs in both consumer and high-performance applications, providing enterprise-level performance while lowering the total cost of ownership. Potential applications include multi-function printers, servers, set-top boxes and solid state drives. The entire family is compliant with PCIe generations 1, 2, and 3.

IDT plans to quickly follow this initial offering with 3.3 V versions of low-power PCIe buffers and multiplexers that are pin-compatible to the successful 9DBU/V and 9DMU/V families.

The 9FGL PCIe clock generator family includes devices with 2, 4, 6, or 8 outputs. The clock generators support both the PCIe Common Clock architecture with or without spread spectrum, and the PCIe Independent Reference (IR) clock architecture (non-spreading). The devices also provide a copy of the reference clock, saving a crystal in the design.

Features
  • 1 - 3.3 V LVCMOS REF output with wake-on-LAN (WOL) support
  • Direct connection to 100Ω (xx41) or 85Ω (xx51) transmission lines; saves 24 resistors compared to standard PCIe devices
  • SMVus-selectable features allows optimization to customer requirements
  • 41 and 51 devices contain default configuration; SMBus interface not required for device operation
  • OE# pins; support DIF power management
  • Two selectable SMBus addresses; multiple devices can easily share an SMBus segment
  • P1 device allows factory programming of customer-defined SMBus power up default; allows exact optimization to customer requirements
  • DIF outputs blocked until PLL is locked; clean system start-up
  • Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF outputs; minimize EMI and phase jitter for each application
  • 25 MHz default input frequency; external crystal such as the IDT 603-25-150 (25 MHz); supports tight ppm with 0 ppm synthesis error
  • Space saving package; minimal board space

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