ECP5™ SERDES Enabled FPGA Family

By Lattice Semiconductor Corporation 56

ECP5™ SERDES Enabled FPGA Family

Designers  of equipment for many emerging high-volume applications are blending FPGAs with ASICs and ASSPs to rapidly build flexible systems that meet tight cost, power, and form factor constraints. In developing the ECP5 FPGA family, Lattice breaks the rule that all FPGAs should be the highest density, power hungry, and expensive. With a focus on compact, high-volume applications, Lattice optimized the ECP5 architecture for low-cost, small form-factor, and low-power consumption. These characteristics make the ECP5 devices ideal for delivering programmable connectivity solutions to complement ASICs and ASSPs.

Video - ECP5 FPGA Family

Features
  • 270 Mbps to 3.2 Gbps for generic 8b10b, 10-bit SERDES, and 8-bit SERDES modes
  • Up to 4 channels per device in dual channel blocks for higher granularity
  • Enhanced DSP blocks provide 2x resource improvement for symmetrical filters
  • Low static power typically under 80 mW and low dynamic power with 1.1 V core voltage
  • Programmable IO support for LVCMOS 33/25/18/15/12, XGMII, LVTTL, LVDS, Bus-LVDS, 7:1 LVDS, LVPECL, and MIPI D-PHY input interfaces

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