Microchip's 16-bit, PIC24 MCUs and dsPIC® digital signal controllers provide designers with an easy upgrade path from 8-bit PIC® microcontrollers and a cost-effective option to 32-bit MCUs. The broad product line includes everything from eXtreme low power microcontrollers to high-performance digital signal controllers. With single-cycle execution, deterministic interrupt response, zero overhead looping, and fast DMA, the dsPIC family also adds a single-cycle 16 x 16 MAC and 40-bit accumulators. These are ideal for math intensive applications like motor control and digital power.
Combined with hardware and free software, these 16-bit products are ideal for designs including high-efficiency motor control, platinum-rated digital power supplies, and low power for longer battery life in portable applications. Integrated touch and display features help lower costs and simplify designs for user interfaces including mTouch™ sensing, graphics, and segmented display drivers. Specialized peripherals and software for connectivity such as USB, CAN, and wireless protocols make it easy to communicate with other systems.
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- Cryptographic engine
- Performs NIST standard encryption / decryption operations without CPU intervention
- DES / 3DES cipher support, with up to three unique keys for 3DES
- Supports ECB, CBC, OFB, CTR, and CFB128 modes
- Programmatically secure OTP array for key storage
- True random number generation
- Battery-backed RAM key storage
- Extreme low-power
- Multiple power management options for extreme power reduction
- VBAT allows for lowest power consumption on backup battery (with or without RTCC)
- Deep sleep allows near total power-down with the ability to wake-up on external triggers
- Sleep and idle modes selectively shut down peripherals and/or core for substantial power reduction and fast wake-up
- Doze mode allows CPU to run at a lower clock speed than peripherals
- Alternate clock modes allow on-the-fly switching to a lower clock speed for selective power reduction
- Extreme low-power current consumption for deep sleep
- WDT: 650 nA at 2 V (typ.)
- RTCC: 650 nA at 32 kHz, 2 V (typ.)
- Deep sleep current, 60 nA (typ.)
- 160 µA / MHz in run mode
- Dual-partition Flash with live update capability
- Capable of holding two independent software applications, including bootloader
- Permits simultaneous programming of one partition while executing application code from the other
- Allows run-time switching between active partitions
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- CPU
- Modified Harvard architecture
- Up to 16 MIPS operation at 32 MHz
- 8 MHz internal oscillator:
- 96 MHz PLL option
- Multiple clock divide options
- Run-time self-calibration capability for maintaining better than ±0.20% accuracy
- Fast start-up
- 7-bit x 17-bit single-cycle hardware fractional/integer multiplier
- 32-bit x 16-bit hardware divider
- 16-bit x 16-bit working register array
- C compiler optimized instruction set architecture
- Two address generation units for separate read and write addressing of data memory
- Analog features
- 10/12-bit, up to 24-channel analog-to-digital (A/D) converter:
- Conversion rate of 500 ksps (10-bit), 200 kbps (12-bit)
- Auto-scan and threshold compare features
- Conversion available during sleep
- One 10-bit digital-to-analog converter (DAC):
- Three rail-to-rail, enhanced analog comparators with programmable input / output configuration
- Charge time measurement unit (CTMU):
- Used for capacitive touch sensing, up to 24 channels
- Time measurement down to 100 ps resolution
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