The Cypress HyperFlash family of products are high-speed, CMOS, MirrorBit® NOR Flash devices with the HyperBus, low signal count, DDR (double data rate) interface that achieve high-speed read throughput. The DDR protocol transfers two data bytes per clock cycle on the data (DQ) signals. A read or write access for the HyperFlash consists of a series of 16-bit-wide, one-clock-cycle data transfers at the internal HyperFlash core, and two corresponding 8-bit-wide, one-half-clock-cycle data transfers on the DQ signals.

Both data and command/address information are transferred in DDR fashion over the 8-bit data bus. The clock input signals are used for signal capture by the HyperFlash device when receiving command/address/data information on the DQ signals. The read write data strobe (RWDS) is an output from the HyperFlash device that indicates when data is being transferred from the memory to the host. RWDS is referenced to the rising and falling edges of CK during the data transfer portion of read operations. Command/address/write-data values are center aligned with the clock edges, and read-data values are edge aligned with the transitions of RWDS.

Read and write operations to the HyperFlash device are burst oriented. Read transactions can be specified to use either a wrapped or linear burst. During wrapped operation, accesses start at a selected location and continue for a configured number of locations in a group wrap sequence. During linear operation, accesses start at a selected location and continue in a sequential manner until the read operation is terminated, when CS# returns high. Write transactions transfer one or more 16-bit values.

The HyperFlash family consists of multiple densities, 1.8 V or 3.0 V core and I/O, non-volatile, synchronous Flash memory devices. The devices are qualified to the highest standards, including automotive AEC-Q100 qualification with support for temperatures that range from -40°C to 125°C.