The DDR4 SDRAM, from ISSI, Integrated Silicon Solution Inc., is a high-speed, dynamic, random-access memory internally configured as sixteen banks, four bank groups with four banks for each bank group (for x4/x8), and eight banks, 2 bank groups with 4 banks for each bank group (for x16 DRAM). The DDR4 SDRAM uses an 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit-wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR4 SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight or a ”chopped” burst of four in a programmed sequence. Operation begins with the registration of an ACTIVATE command which is then followed by a Read or Write command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be activated (BG0-BG1 in x4/8 and BG0 in x16 select the bank group, BA0-BA1 select the bank, and A0-A14 select the row) . The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto-precharge command is to be issued (via A10), and select BC4 or BL8 mode ”on the fly” (via A12) if enabled in the mode register.