LMK04208, Ultra-Low-Noise Clock Jitter Cleaner

LMK04208, Ultra-Low-Noise Clock Jitter Cleaner

Texas Instruments' LMK04208 is a high performance clock conditioner offering superior clock jitter cleaning, generation, and distribution with advanced features to meet next-generation system requirements. The dual-loop PLLatinum™ architecture is capable of 111 fs RMS jitter (12 kHz to 20 MHz) using a low-noise VCXO module or sub-200 fs RMS jitter (12 kHz to 20 MHz) using a low-cost, external crystal and varactor diode.

The dual-loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very-narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module, or the tunable crystal, to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2, where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz), where the integrated VCO outperforms the VCXO module, or tunable crystal, used in PLL1.

  • Ultra-low RMS jitter performance 
    • 111 fs RMS jitter (12 kHz to 20 MHz)
    • 123 fs RMS jitter (100 Hz to 20 MHz)
  • PLL1 
    • Integrated, low-noise crystal oscillator circuit
    • Holdover mode when input clocks are lost 
      • Automatic or manual triggering/recovery
  • PLL2
    • Normalized PLL noise floor of -227 dBc/Hz
    • Phase detector rate of up to 155 MHz
    • OSCin frequency-doubler
    • Integrated, low-noise VCO or external VCO mode
  • Two redundant input clocks with LOS
    • Automatic and manual switch-over modes
  • Dual-loop PLLatinum™ PLL architecture 
  • 50 % duty cycle output divides, 1 to 1045 (even and odd)
  • Six LVPECL, LVDS, or LVCMOS programmable outputs
  • Digital delay: fixed or dynamically adjustable
  • 25 ps step analog delay control
  • Seven differential outputs, up to 14 single-ended 
    • Up to six VCXO/crystal buffered outputs
  • Clock rates of up to 1536 MHz
  • 0-delay mode
  • Three default clock outputs at power up
  • Multi-mode: dual PLL, single PLL, and clock distribution
  • Industrial temperature range: -40°C to 85°C
  • 3.15 V to 3.45 V operation
  • 64-pin WQFN package (9.0 mm × 9.0 mm × 0.8 mm)

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