NXP's S32K144EVB evaluation board provides a low-cost platform tor prototyping and demonstration for the S32K144 AEC-Q100 qualified MCU family. The board allows flexible power supply options as well as easy header pin access to the ARM Cortex-M4F, 512 KB Flash MCUs. All family members are designed in accordance with the ISO 26262 standard, AEC-Q100 qualified at up to 125°C, and guaranteed by NXP’s product longevity program which assures supply for a minimum of 15 years.

Webinar: Getting Started with S32K
Design Studio: S32DS: S32 Design Studio IDE
Video: New S32k MCU Platform for Automotive Applications

S32K144EVB Eval Board Features

• Small form factor
• On-board connectivity for CAN, LIN, UART / SCI
• Arduino™ UNO footprint-compatible expansion "shield" support
• Integrating an SBC (UJA1169) and LIN phy (TJA1027)
• Easy access to the MCU I/O header pins for prototyping
• Potentiometer, RGB LED, two touch pads, and 2x push buttons
• Integrated open-standard serial and debug adapter (OpenSDA) with support for several industry-standard debug interfaces
• Flexible power supply options (microUSB or external 12 V supply)

S32K144 Portfolio Features

• High performance ARM Cortex-M4F up to 112 MHz, IEEE-754 floating point unit (FPU)
• Software friendly architecture
  • 512 KB Flash and 64 KB RAM with ECC on both, 4 KB cache, 4 KB EEPROM (FlexMemory)
  • Independent CPU and peripheral clocking
  • External 8 MHz to 40 MHz crystal oscillator or resonator
  • Up to DC- 60 MHz external square wave input clock
  • Internal clock references
• Connectivity and communications
  • 3x ISO 11898-7 compliant FlexCAN controllers. One controller with flexible data (FD) rate support at 2 Mb/s in normal mode and 8 Mb/s in programming mode with 64 bytes message payload. Suitable for dedicated CAN-FD networks or mixed CAN/CAN-FD networks
• Cryptographic services engine compact (CSEc) hardware security
  • Dedicated security co-processor
  • SHE spec. compliant
  • Secure key storage, AES-128 encryption and decryption, cipher-based message authentication code (CMAC) algorithms, secure boot functions
• Low-power consumption
  • Low leakage 90 nm TFS technology
  • Multiple low power operating modes and IRC combinations - RUN, very low Power RUN (VLPR), STOP, very low power stop (VLPS), current consumption from 29 µA at 25°C in VLPS with a recovery time of 5 µs. All register contents maintained in all power modes
• Analogue and timing
  • 2 x 16-ch 12-bit ADCs at 1 Msps, analogue comparator
  • 4 x 8-ch 16-bit flex timers - IC / OC / PWM modes, fault detection, dead-time insertion, quadrature decode
  • Low power timer, real time clock, programmable delay block for analogue/timer module triggering
• Voltage range: 2.7 V to 5.5 V