ISSI's IS43LD16640C/32320C are 1 Gbit CMOS LPDDR2 DRAMs. The devices are organized as eight banks of 8 Meg words of 16-bits or 4 Meg words of 32-bits. These products use a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 4N pre-fetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. They offer fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 4N bits pre-fetched to achieve very high bandwidth.
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- Low-voltage core and I/O power supplies
- VDD2 = 1.14 V to 1.30 V
- VDDCA/VDDQ = 1.14 V to 1.30 V
- VDD1 = 1.70 V to 1.95 V
- High speed unterminated logic (HSUL_12) I/O interface
- Clock frequency range:
- 10 MHz to 533 MHz (data rate range: 20 Mbps to 1066 Mbps per I/O)
- 4-bit pre-fetch DDR architecture
- Multiplexed, double-data-rate, command/address inputs
- Four or eight internal banks for concurrent operation
Options
Clock Frequencies
Temperature Grades
- Commercial (0°C to 85°C)
- Industrial (-40°C to 85°C)
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- Bidirectional/differential data strobe per byte of data (DQS/DQS#)
- Programmable read/write latencies (RL/WL) and burst lengths (4,8, or 16)
- Per-bank refresh for concurrent operation
- ZQ calibration
- On-chip temperature sensor to control self-refresh rate
- Partial - array self-refresh (PASR)
- Bank and segment masking
- Deep power-down mode (DPD)
- Long-term support
Densities
- 8 Gb
- 4 Gb
- 2 Gb
- 1 Gb
- 512 Mb
- 256 Mb
Package
- 134-ball
- 168-ball PoP BGA
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