Nexperia's AXP family of Si-gate CMOS devices uses leading low threshold process technology and next generation packaging technology to create extremely small functions that support the trend to very low operating voltage and consume very little power. The AXP translators are level translating gates targeted at small footprint portable applications. They are available in single (1G), dual (2G), and triple (3G) gate mini logic formats. Multiple standard and configurable logic functions are included in the AXP translators. These are made available in the industries smallest packages.

AXP logic level translating gates address the control logic interface requirement of driving higher voltage applications. With their wide supply voltage range, these translating gates can be used to interface modern low power control logic at the supply range nodes of 2.5 V, 1.8 V, 1.2 V, or 0.8 V to systems operating at supply voltage nodes of 5.0 V, 3.3 V, 2.5 V, 1.8 V, or 1.2 V. This further supports the migration of applications or sub-systems to lower voltage nodes in order to maximize power savings. The AXP family is the lowest power logic family; likewise, the AXP level translating gates are the lowest power voltage translators available.

AXP translators are available in industry-standard leaded PicoGate and leadless MicroPak packages. This makes them suitable for volume constrained (area and height) portable applications, such as smart-phones and tablet PCs. The lower gate count mini logic products reduce time-to-market by making it easy to implement last-minute changes. They also improve the cost-effectiveness of crowded layouts by simplifying routing and eliminating dependencies in intricate line-layout patterns.

Leaflet: AXP Logic Translators