CTS Corporation announces a new family of phase-lock-loop (PLL) timing modules to address the need for a small size, high performance, and low cost jitter attenuator in applications that require exceptionally clean timing signals. Applications such as fiber-optics, communication systems, test and measurement, radar systems, MRI, and digital video all benefit from this technology intended to reduce the magnitude of jitter or undesired deviation from an ideal timing signal within wireless communication between devices.

As technology continues to evolve, demand has increased for high-speed data transmissions. This requires equipment manufacturers to design hardware that is capable of operating at higher transmission bit rates, thus transmitting data quickly to accommodate trends such as streaming video or geo-location (GPS) based applications.

By utilizing a single ASIC, CTS was able to eliminate multiple other active components previously required to achieve comparable levels of performance. As a result, CTS now offers a best in-class solution that not only achieves small size, high performance, and low cost objectives, but also offers faster time to market and faster prototyping to manufacturers.