MEC1705 Arm® Cortex®-M4F Controller

MEC1705 Arm® Cortex®-M4F Controller

The MEC1705 from Microchip Technology is a customized Arm Cortex-M4F controller for embedded and industrial computing platforms. The MEC170x products are designed to operate as either a stand-alone I/O device or as an EC base component of a split-architecture advanced I/O controller system which uses BC-Link communication protocol to access up to two BC bus companion components. The BC-Link protocol is peer-to-peer, providing communication between the MEC170x embedded controller and registers located in a companion device. The MEC1705 has 2 UARTS and includes EEPROM. The MEC17xx family is a highly-configurable, mixed signal, advanced I/O controller architecture. Every device in the family incorporates a 32-bit Arm Cortex-M4F microcontroller core with a closely-coupled SRAM for code and data. A secure bootloader is used to download the custom firmware image from the system’s shared serial peripheral interface (SPI) Flash device, thereby allowing system designers to customize the device’s behavior. It is available in an extended temperature range of -40°C to +85°C.

The MEC170x products may be configured to communicate with the system host through one of three host interfaces: Intel® Low Pin Count (LPC), Enhanced Serial Peripheral Interface (eSPI), or I2C. The MEC170x products are designed to operate as either a stand-alone I/O device or as an EC base component of a split-architecture advanced I/O controller system which uses BC-Link communication protocol to access up to two BC bus companion components. The MEC170x family of devices offer a software development system interface that includes a trace FIFO debug port, a host accessible serial debug port with a 16C550A register interface, a port 80 BIOS debug port, and a JTAG/SWD debug interface.

Additional Features
  • Arm Cortex-M4F processor core
  • Complete Arm-standard debug support
  • Comprehensive Arm-standard trace support
  • Internal memory: up to 480 KB of SRAM
  • Intel eSPI specification compliant
  • Supports LPC bus frequencies of 19 MHz to 33 MHz
  • Four EC-based SMBus 2.0 host controllers
  • Five independent hardware-driven PS/2 ports
  • One quad SPI controller
  • 18 x 8 interrupt capable multiplexed keyboard scan matrix
  • Four breathing/blinking LED interfaces
  • Multi-purpose AES cryptographic engine: hardware support for ECB, CTR, CBC, and OFB AES modes
  • Cryptographic hash engine: support for SHA-1, SHA-256, SHA-512
  • Public key cryptographic engine: hardware support for RSA and elliptic curve public key algorithms and RSA keys length of 1024-bits or 2048-bits
  • True random number generator: 1 K bit FIFO
  • Monotonic counter
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