The NDB16P is a high-speed CMOS DDR2 synchronous DRAM vetted with Insignis’ proprietary extended test flow to mitigate against early life failures, ensuring premium quality and long-term reliability for industrial use. These devices are designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, write latency = read latency -1, and on-die termination (ODT).

All the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion.

Operating the memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. A sequential and gapless data rate is possible depending on burst length, CAS latency, and speed grade of the device.