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CVMEH22501AMDGGREP

CVMEH22501AMDGGREP
Mfr. #:
CVMEH22501AMDGGREP
Description:
Universal Bus Functions Enhanced Plastics for SN74VMEH22501A
Lifecycle:
New from this manufacturer.
Datasheet:
CVMEH22501AMDGGREP Datasheet
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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ECAD Model:
More Information:
CVMEH22501AMDGGREP more Information CVMEH22501AMDGGREP Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Universal Bus Functions
RoHS:
Y
Minimum Operating Temperature:
- 55 C
Maximum Operating Temperature:
+ 125 C
Package / Case:
TSSOP-48
Packaging:
Reel
Series:
SN74VMEH22501A-EP
Brand:
Texas Instruments
Mounting Style:
SMD/SMT
Product Type:
Universal Bus Functions
Factory Pack Quantity:
2000
Subcategory:
Logic ICs
Unit Weight:
0.009986 oz
Tags
CVME, CVM
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***as Instruments
Enhanced Product 8-Bit Universal Bus Transceiver And Two 1-Bit Bus Transceivers 48-TSSOP -55 to 125
***ical
Bus XCVR Single 10-CH 3-ST 48-Pin TSSOP T/R
***ark
Enhanced Plastics For Sn74vmeh22501a
***i-Key
IC UNIVERSAL BUS TXRX
***AS USD
The SN74VMEH22501A-EP 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is designed for 3.3-V VCC operation with 5-V tolerant inputs. The UBT transceiver allows transparent, latched, and flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide a feedback path for control and diagnostics monitoring. This device provides a high-speed interface between cards operating at LVTTL logic levels and VME64, VME64x, or VME320(2) backplane topologies.
***AS INSRUMENT
The SN74VMEH22501A-EP device is pin-for-pin compatible to the SN74VMEH22501 device (SCES357), but operates at a wider operating temperature range.
***AS INSTRUM
High-speed backplane operation is a direct result of the improved OEC circuitry and high drive that has been designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large capacitive loads and include pseudo-ETL input thresholds (½ VCC ±50 mV) for increased noise immunity. These specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in VITA 1.5.
***
With proper design of a 21-slot VME system, a designer can achieve 320-MB transfer rates on linear backplanes and, possibly, 1-GB transfer rates on the VME320 backplane.
***AS INTRUMENTS
All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs.
***AS INSTRUMENT
Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
***AS INSTRUMEN
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.
***AS INSRUMENT
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, output-enable (OE and OEBY) inputs should be tied to VCC through a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this input.
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Available
On Order:
1984
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