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SN74ABT657ANSR

SN74ABT657ANSR
Mfr. #:
SN74ABT657ANSR
Description:
Bus Transceivers Octal Transceiver
Lifecycle:
New from this manufacturer.
Datasheet:
SN74ABT657ANSR Datasheet
Delivery:
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ECAD Model:
More Information:
SN74ABT657ANSR more Information SN74ABT657ANSR Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Bus Transceivers
RoHS:
Y
Logic Family:
74ABT
Input Level:
TTL
Output Level:
TTL
Output Type:
3-State
High Level Output Current:
- 32 mA
Low Level Output Current:
64 mA
Propagation Delay Time:
4.2 ns
Supply Voltage - Max:
5.5 V
Supply Voltage - Min:
4.5 V
Minimum Operating Temperature:
- 40 C
Maximum Operating Temperature:
+ 85 C
Package / Case:
SO-24
Packaging:
Reel
Function:
Bus Transceiver with Parity Checker
Height:
1.95 mm
Length:
15 mm
Number of Circuits:
8
Product:
BiCMOS
Technology:
BiCMOS
Width:
5.3 mm
Brand:
Texas Instruments
Mounting Style:
SMD/SMT
Number of Channels:
8
Supply Current - Max:
40 mA
Operating Supply Voltage:
4.5 V to 5.5 V
Polarity:
Non-Inverting
Product Type:
Bus Transceivers
Factory Pack Quantity:
1
Subcategory:
Logic ICs
Unit Weight:
0.010857 oz
Tags
SN74ABT657ANS, SN74ABT657AN, SN74ABT657, SN74ABT65, SN74ABT6, SN74AB, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC TRANSCVR TRI-ST 16BIT 24SO
***as Instruments
The 'ABT657A transceivers have eight noninverting buffers with parity-generator/ checker circuits and control signals. The transmit/receive (T/R\) input determines the direction of data flow. When T/R\ is high, data flows from the A port to the B port (transmit mode); when T/R\ is low, data flows from the B port to the A port (receive mode). When the output-enable (OE\) input is high, both the A and B ports are in the high-impedance state. Odd or even parity is selected by a logic high or low level on the ODD/EVEN\ input. PARITY carries the parity-bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode. In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic level that maintains the parity sense selected by the level at ODD/EVEN\. For example, if ODD/EVEN\ is low (even parity selected) and there are five high bits on the A bus, PARITY is set to the logic high level so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high. In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR\) output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example, if ODD/EVEN\ is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR\ is low, indicating a parity error. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT657A is characterized for operation over the full military temperature range of -55C to 125C. The SN74ABT657A is characterized for operation from -40C to 85C.
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Available
On Order:
1500
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