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SN74ABT8652DWRG4

SN74ABT8652DWRG4
Mfr. #:
SN74ABT8652DWRG4
Description:
Specialty Function Logic Scan Test Devices
Lifecycle:
New from this manufacturer.
Datasheet:
SN74ABT8652DWRG4 Datasheet
Delivery:
DHL FedEx Ups TNT EMS
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ECAD Model:
More Information:
SN74ABT8652DWRG4 more Information SN74ABT8652DWRG4 Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Specialty Function Logic
RoHS:
Y
Package / Case:
SOIC-28
Packaging:
Reel
Brand:
Texas Instruments
Mounting Style:
SMD/SMT
Product Type:
Specialty Function Logic
Factory Pack Quantity:
1
Subcategory:
Logic ICs
Unit Weight:
0.078125 oz
Tags
SN74ABT8652DWR, SN74ABT8652DW, SN74ABT865, SN74ABT86, SN74ABT8, SN74AB, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC SCAN TEST DEVICE 28SOIC
***as Instruments
The 'ABT8652 scan test devices with octal bus transceivers and registers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are functionally equivalent to the 'F652 and 'ABT652 octal bus transceivers and registers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal bus transceivers and registers. Data flow in each direction is controlled by clock (CLKAB and CLKBA), select (SAB and SBA), and output-enable (OEAB and ) inputs. For A-to-B data flow, data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). When OEAB is high, the B outputs are active. When OEAB is low, the B outputs are in the high-impedance state. Control for B-to-A data flow is similar to that for A-to-B data flow but uses CLKBA, SBA, and inputs. Since the input is active low, the A outputs are active when is low and are in the high-impedance state when is high. Figure 1 shows the four fundamental bus-management functions that can be performed with the 'ABT8652. In the test mode, the normal operation of the SCOPETM bus transceivers and registers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations as described in IEEE Standard 1149.1-1990. Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. The SN54ABT8652 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT8652 is characterized for operation from -40°C to 85°C.
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