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SN74ABT833NSRE4

SN74ABT833NSRE4
Mfr. #:
SN74ABT833NSRE4
Description:
Bus Transceivers 8-Bit to 9-Bit Parity Bus Xcvr
Lifecycle:
New from this manufacturer.
Datasheet:
SN74ABT833NSRE4 Datasheet
Delivery:
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ECAD Model:
More Information:
SN74ABT833NSRE4 more Information SN74ABT833NSRE4 Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Bus Transceivers
RoHS:
Y
Logic Family:
74ABT
Input Level:
TTL
Output Level:
TTL
Output Type:
3-State
High Level Output Current:
- 32 mA
Low Level Output Current:
64 mA
Supply Voltage - Max:
5.5 V
Supply Voltage - Min:
4.5 V
Minimum Operating Temperature:
- 40 C
Maximum Operating Temperature:
+ 85 C
Package / Case:
SO-24
Packaging:
Reel
Function:
Registered Transceiver with Parity Checker
Height:
1.95 mm
Length:
15 mm
Number of Circuits:
1
Product:
BiCMOS
Quiescent Current:
24 mA
Technology:
BiCMOS
Width:
5.3 mm
Brand:
Texas Instruments
Mounting Style:
SMD/SMT
Number of Channels:
8
Supply Current - Max:
38 mA
Operating Supply Voltage:
4.5 V to 5.5 V
Polarity:
Non-Inverting
Product Type:
Bus Transceivers
Factory Pack Quantity:
1
Subcategory:
Logic ICs
Triggering Type:
Positive Edge
Unit Weight:
0.010857 oz
Tags
SN74ABT833NS, SN74ABT833N, SN74ABT83, SN74ABT8, SN74AB, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC TRANSCVR 8-9BIT INVERT 24SO
***eco
OPEN 98/07/24 <AZ
***as Instruments
The 'ABT833 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error () output indicates whether or not an error in the B data has occurred. The output-enable ( and ) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT833 provide true data at their outputs. A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the flag. is clocked into the register on the rising edge of the clock (CLK) input. The error flag register is cleared with a low pulse on the clear () input. When both and are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. To ensure the high-impedance state during power up or power down, should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT833 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT833 is characterized for operation from -40°C to 85°C.
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Available
On Order:
3500
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