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SN74LVT8996DW

SN74LVT8996DW
Mfr. #:
SN74LVT8996DW
Description:
Specialty Function Logic 3.3V 10-Bit Add Port Multi-Add Tap Trncvr
Lifecycle:
New from this manufacturer.
Datasheet:
SN74LVT8996DW Datasheet
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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ECAD Model:
More Information:
SN74LVT8996DW more Information SN74LVT8996DW Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Specialty Function Logic
RoHS:
Y
Product:
Boundry Scan JTAG Logic
Series:
SN74LVT8996
Operating Supply Voltage:
2.7 V to 3.6 V
Minimum Operating Temperature:
- 40 C
Maximum Operating Temperature:
+ 85 C
Package / Case:
SOIC-24
Packaging:
Tube
Operating Temperature Range:
- 40 C to + 85 C
Brand:
Texas Instruments
Mounting Style:
SMD/SMT
Product Type:
Specialty Function Logic
Factory Pack Quantity:
25
Subcategory:
Logic ICs
Unit Weight:
0.022025 oz
Tags
SN74LVT8996D, SN74LVT899, SN74LVT8, SN74LVT, SN74LV, SN74L, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
    P***i
    P***i
    PL

    OK-polecam!

    2019-01-31
    J***k
    J***k
    CZ

    It's smaller than I expected (that's good). it came in nice safe package. It works fine in Arduino IDE, but I don't know if It works properly (no success indicator - real Arduino have LED indicator). (I will update this rating, when I try it on some HW)

    2019-05-12
***as Instruments
3.3-V ABT 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) TAP Transceiver 24-SOIC -40 to 85
***ical
Addressable Scan Port -40C 85C 24-Pin SOIC Tube
***ark
IC, 10BIT TAP TRANSCEIVER, SOIC-24
***i-Key
IC 10-BIT SCAN PORT XCVR 24-SOIC
*** Stop Electro
Microprocessor Circuit, BICMOS, PDSO24
***i-Key Marketplace
SN74LVT8996 3.3-V ABT 10-BIT ADD
***OMO Electronic
The 'LVT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most SCOPETM devices, the ASP is not a boundary-scannable device, rather, it applies TI's addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level.
***AS USD
These devices are functionally equivalent to the 'ABT8996 ASPs. Additionally, they are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to interface to 5-V masters and/or targets.
***AS
Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP signals to a set of secondary TAP signals - for example, to interface backplane TAP signals to a board-level TAP. The ASP provides all signal buffering that might be required at these two interfaces. When primary and secondary TAPs are connected, only a moderate propagation delay is introduced - no storage/retiming elements are inserted. This minimizes the need for reformatting board-level test vectors for in-system use.
***AS INSTRUMEN
Most operations of the ASP are synchronous to the primary test clock (PTCK) input. PTCK is always buffered directly onto the secondary test clock (STCK) output.
***AS INSTRU
Upon power up of the device, the ASP assumes a condition in which the primary TAP is disconnected from the secondary TAP (unless the bypass signal is used, as below). This reset condition also can be entered by the assertion of the primary test reset (PTRST\) input or by use of shadow protocol. PTRST\ is always buffered directly onto the secondary test reset (STRST\) output, ensuring that the ASP and its associated secondary TAP can be reset simultaneously.
***INS
When connected, the primary test data input (PTDI) and primary test mode select (PTMS) input are buffered onto the secondary test data output (STDO) and secondary test mode select (STMS) output, respectively, while the secondary test data input (STDI) is buffered onto the primary test data output (PTDO). When disconnected, STDO is at high impedance, while PTDO is at high impedance, except during acknowledgment of a shadow protocol. Upon disconnect of the secondary TAP, STMS holds its last low or high level, allowing the secondary TAP to be held in its last stable state. Upon reset of the ASP, STMS is high, allowing the secondary TAP to be synchronously reset to the Test-Logic-Reset state.
***INS
In system, primary-to-secondary connection is based on shadow protocols that are received and acknowledged on PTDI and PTDO, respectively. These protocols can occur in any of the stable TAP states other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset, Run-Test/Idle, Pause-DR or Pause-IR). The essential nature of the protocols is to receive/transmit an address via a serial bit-pair signaling scheme. When an address is received serially at PTDI that matches that at the parallel address inputs (A9-A0), the ASP serially retransmits its address at PTDO as an acknowledgment and then assumes the connected (ON) status, as above. If the received address does not match that at the address inputs, the ASP immediately assumes the disconnected (OFF) status without acknowledgment.
***AS
The ASP also supports three dedicated addresses that can be received globally (that is, to which all ASPs respond) during shadow protocols. Receipt of the dedicated disconnect address (DSA) causes the ASP to disconnect in the same fashion as a nonmatching address. Reservation of this address for global use ensures that at least one address is available to disconnect all receiving ASPs. The DSA is especially useful when the secondary TAPs of multiple ASPs are to be left in different stable states. Receipt of the reset address (RSA) causes the ASP to assume the reset condition, as above. Receipt of the test-synchronization address (TSA) causes the ASP to assume a connect status (MULTICAST) in which PTDO is at high impedance but the connections from PTMS to STMS and PTDI to STDO are maintained to allow simultaneous operation of the secondary TAPs of multiple ASPs. This is useful for multicast TAP-state movement, simultaneous test operation (such as in Run-Test/Idle state), and scanning of common test data into multiple like scan chains. The TSA is valid only when received in the Pause-DR or Pause-IR TAP states.
***AS INS
Alternatively, primary-to-secondary connection can be selected by assertion of a low level at the bypass (BYP\) input. This operation is asynchronous to PTCK and is independent of PTRST\ and/or power-up reset. This bypassing feature is especially useful in the board-test environment, since it allows the board-level automated test equipment (ATE) to treat the ASP as a simple transceiver. When the BYP\ input is high, the ASP is free to respond to shadow protocols. Otherwise, when BYP\ is low, shadow protocols are ignored.
***AS INST
Whether the connected status is achieved by use of shadow protocol or by use of BYP\, this status is indicated by a low level at the connect (CON\) output. Likewise, when the secondary TAP is disconnected from the primary TAP, the CON\ output is high.
***INS
The SN54LVT8996 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT8996 is characterized for operation from -40°C to 85°C.
Logic Solutions
OMO Electronic Logic Solutions offers a full spectrum of logic functions and technologies from the mature to the advanced, including bipolar, BiCMOS, and CMOS. TI's process technologies offer the logic performance and features required for modern logic designs, while maintaining support for more traditional logic products.Learn More
Part # Description Stock Price
SN74LVT8996DW
DISTI # 29459052		Addressable Scan Port 24-Pin SOIC Tube
RoHS: Compliant		4050
  • 50:$9.1241
SN74LVT8996DW
DISTI # 296-8656-5-ND		IC 10-BIT SCAN PORT XCVR 24-SOIC
RoHS: Compliant
Min Qty: 50
Container: Tube		Temporarily Out of Stock
  • 50:$13.3330
SN74LVT8996DWR
DISTI # 296-8656-2-ND		IC 10-BIT SCAN PORT XCVR 24-SOIC
RoHS: Compliant
Min Qty: 2000
Container: Tape & Reel (TR)		Temporarily Out of Stock
  • 2000:$6.6790
SN74LVT8996DW
DISTI # SN74LVT8996DW		Addressable Scan Port 24-Pin SOIC Tube (Alt: SN74LVT8996DW)
RoHS: Compliant
Min Qty: 1
Container: Tube		Europe - 0
  • 1:€11.3900
  • 10:€10.8900
  • 25:€10.2900
  • 50:€9.8900
  • 100:€9.3900
  • 500:€8.9900
  • 1000:€8.6900
SN74LVT8996DW
DISTI # SN74LVT8996DW		Addressable Scan Port 24-Pin SOIC Tube - Rail/Tube (Alt: SN74LVT8996DW)
RoHS: Compliant
Min Qty: 75
Container: Tube		Americas - 0
  • 75:$10.3900
  • 125:$9.8900
  • 200:$9.5900
  • 375:$9.1900
  • 750:$8.9900
SN74LVT8996DWR
DISTI # SN74LVT8996DWR		Addressable Scan Port 24-Pin SOIC T/R (Alt: SN74LVT8996DWR)
RoHS: Not Compliant
Min Qty: 1
Container: Tape and Reel		Europe - 0
  • 1:€8.6900
  • 10:€8.1900
  • 25:€7.6900
  • 50:€7.2900
  • 100:€6.8900
  • 500:€6.5900
  • 1000:€6.1900
SN74LVT8996DWR
DISTI # SN74LVT8996DWR		Addressable Scan Port 24-Pin SOIC T/R - Tape and Reel (Alt: SN74LVT8996DWR)
RoHS: Compliant
Min Qty: 2000
Container: Reel		Americas - 0
  • 2000:$7.4900
  • 4000:$7.1900
  • 8000:$6.8900
  • 12000:$6.6900
  • 20000:$6.4900
SN74LVT8996DW
DISTI # 595-SN74LVT8996DW		Specialty Function Logic 3.3V 10-Bit Add Port Multi-Add Tap Trncvr
RoHS: Compliant		0
  • 1:$15.1300
  • 10:$13.9100
  • 25:$13.1900
  • 100:$11.7500
  • 250:$11.1800
  • 500:$10.4600
SN74LVT8996DWR
DISTI # 595-SN74LVT8996DWR		Specialty Function Logic 3.3V 10-Bit Add Port Multi-Add Tap Trncvr
RoHS: Compliant		0
  • 1:$10.9600
  • 10:$10.0700
  • 25:$9.5500
  • 100:$8.5100
  • 250:$8.0900
  • 500:$7.5700
  • 1000:$6.9400
SN74LVT8996DWMicroprocessor Circuit, BICMOS, PDSO24
RoHS: Compliant		262
  • 1000:$9.4900
  • 500:$9.9900
  • 100:$10.4000
  • 25:$10.8400
  • 1:$11.6800
SN74LVT8996DWTEST/JTAG SUPPORT, 24 Pin, Plastic, SOP25
  • 4:$7.5000
  • 2:$10.0000
  • 1:$15.0000
SN74LVT8996DWTEST/JTAG SUPPORT, 24 Pin, Plastic, SOP461
  • 309:$6.0000
  • 72:$6.5000
  • 1:$15.0000
SN74LVT8996DWRTEST/JTAG SUPPORT, 24 Pin, Plastic, SOP3295
  • 780:$3.6750
  • 477:$3.8500
  • 1:$10.5000
SN74LVT8996DWRINSTOCK2232
    SN74LVT8996DWR
    DISTI # SN74LVT8996DWR    		Microprocessor Circuit, BICMOS, PDSO24
    RoHS: Compliant    		7
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      Availability
      Stock:
      Available
      On Order:
      2500
      Enter Quantity:
      Current price of SN74LVT8996DW is for reference only, if you want to get best price, please submit a inquiry or direct email to our sales team sales@omo-ic.com
      Reference price (USD)
      Quantity
      Unit Price
      Ext. Price
      50
      $13.19
      $659.50
      100
      $11.75
      $1 175.00
      250
      $11.18
      $2 795.00
      500
      $10.46
      $5 230.00
      1000
      $9.59
      $9 590.00
      Due to semiconductor in short supply from 2021,below price is the Normal price before 2021.please send inquire to confirm.
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