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SN74ACT7805-25DLR

SN74ACT7805-25DLR
Mfr. #:
SN74ACT7805-25DLR
Description:
FIFO 256 x 18 synchronous FIFO memory
Lifecycle:
New from this manufacturer.
Datasheet:
SN74ACT7805-25DLR Datasheet
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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ECAD Model:
More Information:
SN74ACT7805-25DLR more Information SN74ACT7805-25DLR Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
FIFO
RoHS:
Y
Data Bus Width:
18 bit
Bus Direction:
Unidirectional
Memory Size:
4.5 kbit
Timing Type:
Synchronous
Organization:
256 k x 18
Number of Circuits:
2
Maximum Clock Frequency:
40 MHz
Access Time:
15 ns
Supply Voltage - Max:
5.5 V
Supply Voltage - Min:
4.5 V
Supply Current - Max:
0.4 mA
Minimum Operating Temperature:
0 C
Maximum Operating Temperature:
+ 70 C
Package / Case:
SSOP-56
Packaging:
Reel
Height:
2.59 mm
Width:
7.49 mm
Brand:
Texas Instruments
Mounting Style:
SMD/SMT
Operating Supply Voltage:
4.5 V to 5.5 V
Product Type:
FIFO
Factory Pack Quantity:
1
Subcategory:
Memory & Data Storage
Unit Weight:
0.024508 oz
Tags
SN74ACT7805-2, SN74ACT7805, SN74ACT780, SN74ACT78, SN74ACT7, SN74ACT, SN74AC, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***et
FIFO Mem Sync Dual Width Uni-Dir 256 x 18 56-Pin SSOP T/R
***i-Key
IC SYNC FIFO MEM 256X18 56-SSOP
***as Instruments
The SN74ACT7805 is a 256-word 18-bit clocked FIFO suited for buffering asynchronous data paths up to 67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and IR is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and OR is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the input-ready (IR), output-ready (OR), and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7805 is characterized for operation from 0C to 70C.
Part # Description Stock Price
SN74ACT7805-25DLR
DISTI # 296-4457-2-ND		IC SYNC FIFO MEM 256X18 56-SSOP
RoHS: Compliant
Min Qty: 1000
Container: Tape & Reel (TR)		Limited Supply - Call
    SN74ACT7805-25DLR
    DISTI # 296-4457-1-ND    		IC SYNC FIFO MEM 256X18 56-SSOP
    RoHS: Compliant
    Min Qty: 1
    Container: Cut Tape (CT)    		Limited Supply - Call
      SN74ACT7805-25DLR
      DISTI # 296-4457-6-ND      		IC SYNC FIFO MEM 256X18 56-SSOP
      RoHS: Compliant
      Min Qty: 1
      Container: Digi-Reel®      		Limited Supply - Call
        SN74ACT7805-25DLR
        DISTI # 595-SN74ACT780525DLR        		FIFO 256 x 18 synchronous FIFO memory
        RoHS: Compliant        		0
          SN74ACT7805-25DLR 250
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            Availability
            Stock:
            Available
            On Order:
            3000
            Enter Quantity:
            Current price of SN74ACT7805-25DLR is for reference only, if you want to get best price, please submit a inquiry or direct email to our sales team sales@omo-ic.com
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