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SN74ALVC7813-40DL

SN74ALVC7813-40DL
Mfr. #:
SN74ALVC7813-40DL
Description:
FIFO 16-Bit Buffer/Driver With 3-State Outputs
Lifecycle:
New from this manufacturer.
Datasheet:
SN74ALVC7813-40DL Datasheet
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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ECAD Model:
More Information:
SN74ALVC7813-40DL more Information SN74ALVC7813-40DL Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
FIFO
RoHS:
Y
Data Bus Width:
18 bit
Bus Direction:
Unidirectional
Memory Size:
1.125 kbit
Timing Type:
Synchronous
Organization:
64 k x 18
Number of Circuits:
2
Maximum Clock Frequency:
25 MHz
Access Time:
20 ns
Supply Voltage - Max:
3.6 V
Supply Voltage - Min:
3 V
Supply Current - Max:
0.04 mA
Minimum Operating Temperature:
0 C
Maximum Operating Temperature:
+ 70 C
Package / Case:
SSOP-56
Packaging:
Tube
Height:
2.59 mm
Width:
7.49 mm
Brand:
Texas Instruments
Mounting Style:
SMD/SMT
Operating Supply Voltage:
3 V to 3.6 V
Product Type:
FIFO
Factory Pack Quantity:
1
Subcategory:
Memory & Data Storage
Unit Weight:
0.024508 oz
Tags
SN74ALVC7813, SN74ALVC781, SN74ALVC7, SN74ALVC, SN74ALV, SN74AL, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***et
FIFO Mem Sync Dual Width Uni-Dir 64 x 18 56-Pin SSOP Tube
***pNet
FIFO Mem Dual Width Uni-Dir 64 x 18 56-Pin SSOP
***i-Key
IC 64X18 SYNC FIFO MEM 56-SSOP
***as Instruments
The SN74ALVC7813 is suited for buffering asynchronous data paths up to 50-MHz clock rates and 13-ns access times. This device is designed for 3-V to 3.6-V VCC operation. Two devices can be configured for bidirectional data buffering without additional logic. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET\) must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ALVC7813 is characterized for operation from 0C to 70C.
Part # Description Stock Price
SN74ALVC7813-40DL
DISTI # 296-5171-5-ND		IC 64X18 SYNC FIFO MEM 56-SSOP
RoHS: Compliant
Min Qty: 80
Container: Tube		Limited Supply - Call
    SN74ALVC7813-40DLR
    DISTI # SN74ALVC7813-40DLR-ND    		IC MEMORY FIFO 64X18 56-SSOP
    RoHS: Compliant
    Min Qty: 1000
    Container: Tape & Reel (TR)    		Limited Supply - Call
      SN74ALVC7813-40DL
      DISTI # 595-SN74ALVC781340DL      		FIFO 16-Bit Buffer/Driver With 3-State Outputs
      RoHS: Compliant      		0
        SN74ALVC7813-40DLR
        DISTI # 595-SN74ALVC7813-40D        		FIFO 64 x 18 3.3-V Synch FIFO Memory
        RoHS: Compliant        		0
          SN74ALVC7813-40DLFIFO, 64X18, 20ns, Synchronous, CMOS, PDSO56
          RoHS: Compliant          		1494
          • 1000:$5.7800
          • 500:$6.0800
          • 100:$6.3300
          • 25:$6.6000
          • 1:$7.1100
          SN74ALVC7813-40DLRFIFO, 64X18, 20ns, Synchronous, CMOS, PDSO56
          RoHS: Compliant          		1000
          • 1000:$5.7800
          • 500:$6.0800
          • 100:$6.3300
          • 25:$6.6000
          • 1:$7.1100
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          Availability
          Stock:
          Available
          On Order:
          1000
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