SN74ACT7813-20DLR

SN74ACT7813-20DLR
Mfr. #:
SN74ACT7813-20DLR
Description:
FIFO 64 x 18 synchronous FIFO memory
Lifecycle:
New from this manufacturer.
Datasheet:
SN74ACT7813-20DLR Datasheet
Delivery:
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Payment:
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ECAD Model:
More Information:
SN74ACT7813-20DLR more Information SN74ACT7813-20DLR Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
FIFO
RoHS:
Y
Package / Case:
SSOP-56
Packaging:
Reel
Brand:
Texas Instruments
Mounting Style:
SMD/SMT
Operating Supply Voltage:
4.5 V to 5.5 V
Product Type:
FIFO
Factory Pack Quantity:
1
Subcategory:
Memory & Data Storage
Unit Weight:
0.024508 oz
Tags
SN74ACT7813-2, SN74ACT7813, SN74ACT781, SN74ACT78, SN74ACT7, SN74ACT, SN74AC, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***et
FIFO Mem Sync Dual Width Bi-Dir 64 x 18 56-Pin SSOP T/R
***i-Key
IC CLOCKED FIFO 64X18 56-SSOP
***as Instruments
The SN74ACT7813 is a 64-word 18-bit FIFO suited for buffering asynchronous datapaths up to 67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7813 is characterized for operation from 0C to 70C.
Part # Description Stock Price
SN74ACT7813-20DLR
DISTI # SN74ACT7813-20DLR-ND
IC CLOCKED FIFO 64X18 56-SSOP
RoHS: Compliant
Min Qty: 1000
Container: Tape & Reel (TR)
Limited Supply - Call
    SN74ACT7813-20DLR
    DISTI # 595-SN74ACT781320DLR
    FIFO 64 x 18 synchronous FIFO memory
    RoHS: Compliant
    0
      SN74ACT7813-20DLRFIFO, 64X18, 13ns, Synchronous, CMOS, PDSO56
      RoHS: Compliant
      1000
      • 1000:$6.9300
      • 500:$7.3000
      • 100:$7.6000
      • 25:$7.9300
      • 1:$8.5300
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      Availability
      Stock:
      Available
      On Order:
      5500
      Enter Quantity:
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