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SN74S373DWRE4

SN74S373DWRE4
Mfr. #:
SN74S373DWRE4
Description:
Latches Octal D Type Transp Latches
Lifecycle:
New from this manufacturer.
Datasheet:
SN74S373DWRE4 Datasheet
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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ECAD Model:
More Information:
SN74S373DWRE4 more Information SN74S373DWRE4 Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Latches
RoHS:
Y
Number of Circuits:
8 Circuit
Logic Type:
D-Type Transparent Latch
Logic Family:
S
Polarity:
Non-Inverting
Number of Output Lines:
8 Line
High Level Output Current:
- 6.5 mA
Low Level Output Current:
32 mA
Propagation Delay Time:
12 ns at 5 V
Supply Voltage - Max:
5.25 V
Supply Voltage - Min:
4.75 V
Minimum Operating Temperature:
0 C
Maximum Operating Temperature:
+ 70 C
Package / Case:
SOIC-20
Packaging:
Reel
Function:
Transparent
Height:
2.35 mm
Length:
12.8 mm
Output Type:
3-State
Type:
D-Type
Width:
7.52 mm
Brand:
Texas Instruments
Mounting Style:
SMD/SMT
Number of Channels:
8 Channels
Number of Input Lines:
8 Line
Operating Supply Current:
160 mA
Operating Supply Voltage:
5 V
Product Type:
Latches
Reset Type:
No Reset
Factory Pack Quantity:
1
Subcategory:
Logic ICs
Unit Weight:
0.019048 oz
Tags
SN74S373D, SN74S373, SN74S37, SN74S3, SN74S, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC OCT TRANSP D-TYP LATCH 20SOIC
***as Instruments
These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up. The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs. Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.
Part # Description Stock Price
SN74S373DWRE4
DISTI # SN74S373DWRE4-ND		IC OCT TRANSP D-TYP LATCH 20SOIC
RoHS: Compliant
Min Qty: 2000
Container: Tape & Reel (TR)		Limited Supply - Call
    SN74S373DWRE4
    DISTI # 595-SN74S373DWRE4    		Latches Octal D Type Transp Latches
    RoHS: Compliant    		0
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      Mfr.#: SN74S37DRE4

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      Availability
      Stock:
      Available
      On Order:
      4500
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