SN74ACT7805-20DLR

SN74ACT7805-20DLR
Mfr. #:
SN74ACT7805-20DLR
Description:
IC CLOCKED FIFO 256X18 56-SSOP
Lifecycle:
New from this manufacturer.
Datasheet:
SN74ACT7805-20DLR Datasheet
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ECAD Model:
More Information:
SN74ACT7805-20DLR more Information SN74ACT7805-20DLR Product Details
Product Attribute
Attribute Value
Manufacturer
Texas Instruments
Product Category
Logic - FIFOs Memory
Series
74ACT
Packaging
Tape & Reel (TR)
Package-Case
56-BSSOP (0.295", 7.50mm Width)
Operating-Temperature
0°C ~ 70°C
Mounting-Type
Surface Mount
Function
Synchronous
Voltage-Supply
4.5 V ~ 5.5 V
Supplier-Device-Package
56-SSOP
Memory-Size
4.5K (256 x 18)
Data-Rate
50MHz
Access-Time
13ns
Current-Supply-Max
400μA
Bus-Directional
Uni-Directional
Expansion-Type
Width
Programmable-Flags-Support
Yes
Retransmit-Capability
No
FWFT-Support
No
Tags
SN74ACT7805-2, SN74ACT7805, SN74ACT780, SN74ACT78, SN74ACT7, SN74ACT, SN74AC, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
    H***n
    H***n
    SA

    nice

    2019-05-26
    F***m
    F***m
    BE

    ok

    2019-04-08
***et
FIFO Mem Sync Dual Width Uni-Dir 256 x 18 56-Pin SSOP T/R
***i-Key
IC CLOCKED FIFO 256X18 56-SSOP
***as Instruments
The SN74ACT7805 is a 256-word 18-bit clocked FIFO suited for buffering asynchronous data paths up to 67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and IR is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and OR is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the input-ready (IR), output-ready (OR), and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7805 is characterized for operation from 0C to 70C.
Part # Description Stock Price
SN74ACT7805-20DLR
DISTI # SN74ACT7805-20DLR-ND
IC CLOCKED FIFO 256X18 56-SSOP
RoHS: Compliant
Min Qty: 1000
Container: Tape & Reel (TR)
Limited Supply - Call
    SN74ACT7805-20DLR
    DISTI # 595-SN74ACT780520DLR
    FIFO 256 x 18 synchronous FIFO memory
    RoHS: Compliant
    0
      SN74ACT7805-20DLRFIFO, 256X18, 13ns, Synchronous, CMOS, PDSO56
      RoHS: Compliant
      36750
      • 1000:$15.7100
      • 500:$16.5400
      • 100:$17.2200
      • 25:$17.9600
      • 1:$19.3400
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      Availability
      Stock:
      Available
      On Order:
      2500
      Enter Quantity:
      Current price of SN74ACT7805-20DLR is for reference only, if you want to get best price, please submit a inquiry or direct email to our sales team sales@omo-ic.com
      Reference price (USD)
      Quantity
      Unit Price
      Ext. Price
      1
      $0.00
      $0.00
      10
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      $0.00
      100
      $0.00
      $0.00
      500
      $0.00
      $0.00
      1000
      $0.00
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      Due to semiconductor in short supply from 2021,below price is the Normal price before 2021.please send inquire to confirm.
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