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SN74LVC823ANSR

SN74LVC823ANSR
Mfr. #:
SN74LVC823ANSR
Description:
Flip Flops 9-Bit Bus Intfc FlipFlop W/3-St Otpt
Lifecycle:
New from this manufacturer.
Datasheet:
SN74LVC823ANSR Datasheet
Delivery:
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ECAD Model:
More Information:
SN74LVC823ANSR more Information SN74LVC823ANSR Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Flip Flops
RoHS:
Y
Number of Circuits:
1
Logic Family:
74LV
Logic Type:
Bus Interface Flip-Flop
Polarity:
Non-Inverting
Input Type:
Single-Ended
Output Type:
Single-Ended
Propagation Delay Time:
8.9 ns
High Level Output Current:
- 24 mA
Low Level Output Current:
24 mA
Supply Voltage - Min:
1.65 V
Supply Voltage - Max:
3.6 V
Minimum Operating Temperature:
- 40 C
Maximum Operating Temperature:
+ 85 C
Mounting Style:
SMD/SMT
Package / Case:
SO-24
Packaging:
Reel
Function:
D-Type Bus Interface
Height:
1.95 mm
Length:
15 mm
Quiescent Current:
10 uA
Width:
5.3 mm
Brand:
Texas Instruments
Number of Channels:
9
Number of Input Lines:
9
Number of Output Lines:
3
Operating Supply Voltage:
1.65 V to 3.6 V
Product Type:
Flip Flops
Reset Type:
Master Reset
Factory Pack Quantity:
1
Subcategory:
Logic ICs
Unit Weight:
0.010857 oz
Tags
SN74LVC823, SN74LVC82, SN74LVC8, SN74LVC, SN74LV, SN74L, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
*** Stop Electro
Bus Driver, LVC/LCX/Z Series, 1-Func, 9-Bit, True Output, CMOS, PDSO24
***i-Key
IC D-TYPE POS TRG SNGL 24SO
***el Nordic
Contact for details
***as Instruments
This 9-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC823A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. With the clock-enable (CLKEN)\ input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high disables the clock buffer, latching the outputs. This device has noninverting data (D) inputs. Taking the clear (CLR)\ input low causes the nine Q outputs to go low, independently of the clock. A buffered output-enable (OE)\ input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or the high-impedance state. OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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Available
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