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SN74ALVC7813-20DLR

SN74ALVC7813-20DLR
Mfr. #:
SN74ALVC7813-20DLR
Description:
FIFO 64 x 18 3.3-V Synch FIFO Memory
Lifecycle:
New from this manufacturer.
Datasheet:
SN74ALVC7813-20DLR Datasheet
Delivery:
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Payment:
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ECAD Model:
More Information:
SN74ALVC7813-20DLR more Information SN74ALVC7813-20DLR Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
FIFO
RoHS:
Y
Package / Case:
SSOP-56
Packaging:
Reel
Brand:
Texas Instruments
Mounting Style:
SMD/SMT
Operating Supply Voltage:
3 V to 3.6 V
Product Type:
FIFO
Factory Pack Quantity:
1
Subcategory:
Memory & Data Storage
Unit Weight:
0.024508 oz
Tags
SN74ALVC7813-2, SN74ALVC7813, SN74ALVC781, SN74ALVC7, SN74ALVC, SN74ALV, SN74AL, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***et
FIFO Mem Sync Dual Width Uni-Dir 64 x 18 56-Pin SSOP T/R
***i-Key
IC 64X18 SYNC FIFO MEM 56-SSOP
***i-Key Marketplace
FIFO, 64X18, 13NS, SYNCHRONOUS
***as Instruments
The SN74ALVC7813 is suited for buffering asynchronous data paths up to 50-MHz clock rates and 13-ns access times. This device is designed for 3-V to 3.6-V VCC operation. Two devices can be configured for bidirectional data buffering without additional logic. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET\) must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ALVC7813 is characterized for operation from 0C to 70C.
Part # Description Stock Price
SN74ALVC7813-20DLR
DISTI # 296-15980-2-ND		IC 64X18 SYNC FIFO MEM 56-SSOP
RoHS: Compliant
Min Qty: 1000
Container: Tape & Reel (TR)		Limited Supply - Call
    SN74ALVC7813-20DLR
    DISTI # 296-15980-1-ND    		IC 64X18 SYNC FIFO MEM 56-SSOP
    RoHS: Compliant
    Min Qty: 1
    Container: Cut Tape (CT)    		Limited Supply - Call
      SN74ALVC7813-20DLR
      DISTI # 296-15980-6-ND      		IC 64X18 SYNC FIFO MEM 56-SSOP
      RoHS: Compliant
      Min Qty: 1
      Container: Digi-Reel®      		Limited Supply - Call
        SN74ALVC7813-20DLR
        DISTI # 595-SN74ALVC7813-20D        		FIFO 64 x 18 3.3-V Synch FIFO Memory
        RoHS: Compliant        		0
          SN74ALVC7813-20DLRFIFO, 64X18, 13ns, Synchronous, CMOS, PDSO56
          RoHS: Compliant          		1000
          • 1000:$3.4700
          • 500:$3.6600
          • 100:$3.8100
          • 25:$3.9700
          • 1:$4.2800
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          Availability
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          Available
          On Order:
          3000
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