LMK03318RHSR

Mfr. #:: LMK03318RHSR
Description:: Clock Synthesizer / Jitter Cleaner Single PLL clock generator, 8 outputs
Lifecycle:: New from this manufacturer.
Datasheet:: LMK03318RHSR Datasheet
Delivery:: DHL FedEx Ups TNT EMS
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More Information:: LMK03318RHSR more Information LMK03318RHSR Product Details

Product Attribute
Attribute Value

Manufacturer:: Texas Instruments

Product Category:: Clock Synthesizer / Jitter Cleaner

Series:: LMK03318

Minimum Operating Temperature:: - 40 C

Maximum Operating Temperature:: + 85 C

Mounting Style:: SMD/SMT

Package / Case:: WQFN-48

Packaging:: Reel

Brand:: Texas Instruments

Moisture Sensitive:: Yes

Product Type:: Clock Synthesizer / Jitter Cleaner

Factory Pack Quantity:: 2500

Subcategory:: Clock & Timer ICs

Tradename:: PLLatinum

Tags: LMK03318R, LMK0331, LMK033, LMK03, LMK0, LMK

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We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: info@omo-ic.com

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

LMK03318RHSR Description

***as Instruments: Ultra-low jitter clock generator family with single PLL 48-WQFN -40 to 85

***et: PLL Clock Generator Single 1MHz to 1000MHz 48-Pin WQFN T/R

*** Stop Electro: PLL Based Clock Driver, LMK Series, 16 True Output(s), 0 Inverted Output(s), PQCC48

***ark: Single Pll Clock Generator, 8 Outputs

***OMO Electronic: The LMK03318 device is an ultra-low-noise PLLATINUM™ clock generator with one fractional-N frequency synthesizer with integrated VCO, flexible clock distribution and fanout, and pin-selectable configuration states stored in on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices, thus reducing BOM cost and board area and improving reliability by replacing multiple oscillators and clock distribution devices. The ultra-low jitter reduces bit-error rate (BER) in high-speed serial links.

***ASI: For the PLL, a differential clock, a single-ended clock, or a crystal input can be selected as the reference clock. The selected reference input can be used to lock the VCO frequency at an integer or fractional multiple of the reference input frequency. The VCO frequency can be tuned between 4.8 GHz and 5.4 GHz. The PLL offers the flexibility to select a predefined or user-defined loop bandwidth, depending on the needs of the application. The PLL has a post-divider that can be selected between divide-by 2, 3, 4, 5, 6, 7, or 8.

***ASIN: All the output channels can select the divided-down VCO clock from the PLL as the source for the output divider to set the final output frequency. Some output channels can also independently select the reference input for the PLL as an alternative source to be bypassed to the corresponding output buffers. The 8-bit output dividers support a divide range of 1 to 256 (even or odd), output frequencies up to 1 GHz, and output phase synchronization capability.

***ASIN: All output pairs are ground-referenced CML drivers with programmable swing that can be interfaced to LVDS, LVPECL, or CML receivers with AC coupling. All output pairs can also be independently configured as HCSL outputs or 2 × 1.8-V LVCMOS outputs. The outputs offer lower power at 1.8 V, higher performance and power supply noise immunity, and lower EMI compared to voltage-referenced driver designs (such as traditional LVDS and LVPECL drivers). Two additional 3.3-V LVCMOS outputs can be obtained via the STATUS pins. This is an optional feature in case of a need for 3.3-V LVCMOS outputs and device status signals are not needed.

***as Instruments Inc.: The device features self start-up from on-chip programmable EEPROM or pre-defined ROM memory, which offers multiple custom device modes selectable via pin control eliminating the need for serial programming. The device registers and on-chip EEPROM settings are fully programmable through the I2C-compatible serial interface. The device slave address is programmable in EEPROM and LSBs can be set with a 3-state pin.

***AS INSTRU: The device provides two frequency margining options with glitch-free operation to support system design verification tests (DVT), such as standard compliance and system timing margin testing. Fine frequency margining (in ppm) can be supported by using a low-cost pullable crystal on the internal crystal oscillator (XO), and selecting this input as the reference to the PLL synthesizer. The frequency margining range is determined by the trim sensitivity of the crystal and the on-chip varactor range. XO frequency margining can be controlled through pin or I2C control for ease-of use and high flexibility. Coarse frequency margining (in %) is available on any output channel by changing the output divide value via I2C interface, which synchronously stops and restarts the output clock to prevent a glitch or runt pulse when the divider is changed.

***as Instruments (TI): Internal power conditioning provide excellent power supply noise rejection (PSNR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from 3.3-V ± 5% supply and output blocks operate from 1.8-V, 2.5-V, or 3.3-V ± 5% supply.

LMK03318RHSR More Information

LMK03318 Ultra-Low-Noise Jitter Clock Generator: OMO Electronic LMK03318 Ultra-Low-Noise PLLatinum™ Clock Generator is a clock generator with one fractional-N frequency synthesizer with integrated VCO. These also have a flexible clock distribution/fanout, and pin-selectable configuration states stored in on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices. The multiple clock generation reduces BOM cost and board area and improves reliability by replacing multiple oscillators and clock distribution devices. The ultra-low jitter reduces the Bit-Error-Rate (BER) in high-speed serial links. Typical applications include switches and routers, network and telecom line cards, servers and storage systems, and wireless base stations.

Market price

Part #	Description	Stock	Price
LMK03318RHSR DISTI # 31938882	Clock Generator 1000MHz-OUT 48-Pin WQFN EP T/R RoHS: Compliant	1209	1209:$9.3118
LMK03318RHSR DISTI # LMK03318RHSR-ND	ULTRA-LOW-NOISE JITTER CLOCK GEN RoHS: Compliant Min Qty: 2500 Container: Tape & Reel (TR)	Temporarily Out of Stock	2500:$7.8848
LMK03318RHSR DISTI # V39:1801_14245862	Clock Generator 1000MHz-OUT 48-Pin WQFN EP T/R RoHS: Compliant	0
LMK03318RHSR DISTI # LMK03318RHSR	PLL Clock Generator Single 1MHz to 1000MHz 48-Pin WQFN T/R (Alt: LMK03318RHSR) RoHS: Compliant Min Qty: 2500 Container: Tape and Reel	Asia - 0
LMK03318RHSR DISTI # LMK03318RHSR	PLL Clock Generator Single 1MHz to 1000MHz 48-Pin WQFN T/R - Tape and Reel (Alt: LMK03318RHSR) RoHS: Compliant Min Qty: 2500 Container: Reel	Americas - 0	25000:$7.6900 15000:$7.8900 10000:$8.1900 5000:$8.4900 2500:$8.8900
LMK03318RHSR DISTI # LMK03318RHSR	PLL Clock Generator Single 1MHz to 1000MHz 48-Pin WQFN T/R (Alt: LMK03318RHSR) RoHS: Compliant Min Qty: 2500 Container: Tape and Reel	Europe - 0	25000:€7.3900 15000:€7.7900 10000:€8.0900 5000:€8.8900 2500:€9.8900
LMK03318RHST DISTI # 595-LMK03318RHST	Clock Synthesizer / Jitter Cleaner Single PLL clock generator, 8 outputs RoHS: Compliant	350	1:$14.8700 10:$13.6700 25:$12.9700 100:$11.5500 250:$10.9900 500:$10.2800
LMK03318RHSR DISTI # 595-LMK03318RHSR	Clock Synthesizer / Jitter Cleaner Single PLL clock generator, 8 outputs RoHS: Compliant	0	2500:$8.2000

LMK03318RHSR

Step1:Vacuum Packaging with PL

Step2:Anti-Static Bag

Step3:Packaging Boxes

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes