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SN74LV166APWTG4

SN74LV166APWTG4
Mfr. #:
SN74LV166APWTG4
Description:
Counter Shift Registers Parallel Load 8B Shift Registers
Lifecycle:
New from this manufacturer.
Datasheet:
SN74LV166APWTG4 Datasheet
Delivery:
DHL FedEx Ups TNT EMS
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ECAD Model:
More Information:
SN74LV166APWTG4 more Information SN74LV166APWTG4 Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Counter Shift Registers
RoHS:
Y
Counting Sequence:
Serial/Parallel to Serial
Number of Circuits:
1
Number of Bits:
8 bit
Package / Case:
TSSOP-16
Logic Family:
LV
Logic Type:
CMOS
Number of Input Lines:
9
Propagation Delay Time:
23.3 ns, 18.9 ns, 11.9 ns
Supply Voltage - Max:
5.5 V
Minimum Operating Temperature:
- 40 C
Maximum Operating Temperature:
+ 85 C
Packaging:
Reel
Function:
Shift Register
Width:
4.4 mm
Brand:
Texas Instruments
Mounting Style:
SMD/SMT
Number of Output Lines:
1
Operating Supply Voltage:
2.5 V, 3.3 V, 5 V
Product Type:
Counter Shift Registers
Factory Pack Quantity:
1
Subcategory:
Logic ICs
Unit Weight:
0.002169 oz
Tags
SN74LV166AP, SN74LV166, SN74LV16, SN74LV1, SN74LV, SN74L, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC SHIFT REGISTER SGL 8B 16TSSOP
***ark
Register Logic IC; Logic Family:LV-A; Supply Voltage Min:2V; Supply Voltage Max:5.5V; Package/Case:16-TSSOP; No. of Pins:16; Operating Temperature Range:-40°C to +85°C; Input Type:LVTTL; Leaded Process Compatible:Yes ;RoHS Compliant: Yes
***as Instruments
The 'LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V VCC operation. The 'LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR\) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD\) input. When high, SH/LD\ enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR\ overrides all other inputs, including CLK, and resets all flip-flops to zero. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
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Available
On Order:
1500
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