SN74ACT7807-40PAG

SN74ACT7807-40PAG
Mfr. #:
SN74ACT7807-40PAG
Description:
FIFO 2048 x 9 synchronous FIFO memory
Lifecycle:
New from this manufacturer.
Datasheet:
SN74ACT7807-40PAG Datasheet
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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ECAD Model:
More Information:
SN74ACT7807-40PAG more Information SN74ACT7807-40PAG Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
FIFO
RoHS:
Y
Package / Case:
TQFP-64
Packaging:
Tube
Brand:
Texas Instruments
Mounting Style:
SMD/SMT
Moisture Sensitive:
Yes
Operating Supply Voltage:
4.5 V to 5.5 V
Product Type:
FIFO
Factory Pack Quantity:
1
Subcategory:
Memory & Data Storage
Unit Weight:
0.012720 oz
Tags
SN74ACT7807, SN74ACT780, SN74ACT78, SN74ACT7, SN74ACT, SN74AC, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***et
FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 9 64-Pin TQFP Tray
***i-Key
IC SYNC FIFO MEM 2048X9 64-TQFP
***as Instruments
The SN74ACT7807 is a 2048-word by 9-bit FIFO with high speed and fast access times. It processes data at rates up to 67 MHz and access times of 12 ns in a bit-parallel format. Data outputs are noninverting with respect to the data inputs. Expansion is easily accomplished in both word width and word depth. The write-clock (WRTCLK) and read-clock (RDCLK) inputs should be free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when the write-enable (WRTEN1/DP9, WRTEN2) inputs are high and the input-ready (IR) flag output is high. Data is read from memory on the rising edge of RDCLK when the read-enable (RDEN1, RDEN2) and output-enable (OE) inputs are high and the output-ready (OR) flag output is high. The first word written to memory is clocked through to the output buffer regardless of the levels on RDEN1, RDEN2, and OE. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronous to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK cycles occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7807 is characterized for operation from 0C to 70C.
Part # Description Stock Price
SN74ACT7807-40PAG
DISTI # 296-4467-ND
IC SYNC FIFO MEM 2048X9 64-TQFP
RoHS: Compliant
Min Qty: 160
Container: Tray
Limited Supply - Call
    SN74ACT7807-40PAG
    DISTI # 595-SN74ACT780740PAG
    FIFO 2048 x 9 synchronous FIFO memory
    RoHS: Compliant
    0
      SN74ACT7807-40PAGFIFO, 2KX9, 25ns, Synchronous, CMOS, PQFP64
      RoHS: Compliant
      1428
      • 1000:$12.1300
      • 500:$12.7700
      • 100:$13.3000
      • 25:$13.8700
      • 1:$14.9300
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      Availability
      Stock:
      Available
      On Order:
      5000
      Enter Quantity:
      Current price of SN74ACT7807-40PAG is for reference only, if you want to get best price, please submit a inquiry or direct email to our sales team sales@omo-ic.com
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