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SN74LV374ADGVR

SN74LV374ADGVR
Mfr. #:
SN74LV374ADGVR
Description:
Flip Flops Octal Edge-Trig D-Ty F-F W/3-State Otpt
Lifecycle:
New from this manufacturer.
Datasheet:
SN74LV374ADGVR Datasheet
Delivery:
DHL FedEx Ups TNT EMS
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ECAD Model:
More Information:
SN74LV374ADGVR more Information SN74LV374ADGVR Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Flip Flops
RoHS:
Y
Number of Circuits:
8
Logic Family:
74LV
Logic Type:
D-Type Flip-Flop
Polarity:
Non-Inverting
Input Type:
Single-Ended
Output Type:
Single-Ended
Propagation Delay Time:
19.3 ns
High Level Output Current:
- 16 mA
Low Level Output Current:
16 mA
Supply Voltage - Min:
2 V
Supply Voltage - Max:
5.5 V
Minimum Operating Temperature:
- 40 C
Maximum Operating Temperature:
+ 85 C
Mounting Style:
SMD/SMT
Package / Case:
TVSOP-20
Packaging:
Reel
Function:
D-Type Bus Interface
Height:
1.05 mm
Length:
5 mm
Quiescent Current:
20 uA
Width:
4.4 mm
Brand:
Texas Instruments
Number of Channels:
8
Number of Input Lines:
2
Number of Output Lines:
1
Operating Supply Voltage:
2 V to 5.5 V
Product Type:
Flip Flops
Factory Pack Quantity:
1
Subcategory:
Logic ICs
Unit Weight:
0.002123 oz
Tags
SN74LV374AD, SN74LV374A, SN74LV374, SN74LV37, SN74LV3, SN74LV, SN74L, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC D-TYPE POS TRG SNGL 20TVSOP
***ark
Flip-Flop Logic IC; Flip Flop Type:D; Trigger Type:Positive Edge; Output Type:Tri-State Non-Inverted; Supply Voltage Range:2V to 5.5V; Logic Case Style:TVSOP; No. of Pins:20; Operating Temperature Range:-40°C to +85°C ;RoHS Compliant: Yes
***as Instruments
The ’LV374A devices are octal edge-triggered D-type flip-flops designed for 2-V to 5.5-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
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Available
On Order:
4500
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