SN74ALS561ADWE4

SN74ALS561ADWE4
Mfr. #:
SN74ALS561ADWE4
Description:
IC COUNTER BIN 4BIT SYNCH 20SOIC
Lifecycle:
New from this manufacturer.
Datasheet:
SN74ALS561ADWE4 Datasheet
Delivery:
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ECAD Model:
More Information:
SN74ALS561ADWE4 more Information SN74ALS561ADWE4 Product Details
Product Attribute
Attribute Value
Manufacturer
Texas Instruments
Product Category
Logic - Counters, Dividers
Series
74ALS
Packaging
Tube
Package-Case
20-SOIC (0.295", 7.50mm Width)
Operating-Temperature
0°C ~ 70°C
Mounting-Type
Surface Mount
Direction
Down
Voltage-Supply
4.5 V ~ 5.5 V
Supplier-Device-Package
20-SOIC
Number-of-Elements
1
Logic-Type
Binary Counter
Number-of-Bits-per-Element
4
Reset
Asynchronous/Synchronous
Timing
Synchronous
Count-Rate
30MHz
Trigger-Type
Positive Edge
Tags
SN74ALS561AD, SN74ALS561, SN74ALS56, SN74ALS5, SN74ALS, SN74AL, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***ser
Counter ICs Sync 4-Bit Binary Counter W/3-St Otpt
***i-Key
IC COUNTER BIN 4BIT SYNCH 20SOIC
***eco
SYNCHRONOUS 4-BIT COUNTER <AZ
***ark
Counter Logic IC; Logic Family:ALS; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; Package/Case:20-SOIC; No. of Pins:20; Operating Temperature Range:0°C to +70°C; Input Type:TTL; Leaded Process Compatible:Yes; Output Type:TTL ;RoHS Compliant: Yes
***as Instruments
These binary counters are programmable and offer synchronous and asynchronous clearing as well as synchronous and asynchronous loading. All synchronous functions are executed on the positive-going edge of the clock. The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). ACLR\ (direct clear) overrides all other functions of the device, while SCLR\ overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by applying a low level to asynchronous load (ALOAD\) or by the combination of a low level at synchronous load (SLOAD\) and a positive-going clock transition. The counting function is enabled only when enable P (ENP), enable T (ENT), ACLR\, ALOAD\, SCLR\, and SLOAD\ are all high. A high level at the output-enable () input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of OE\. ENT is fed forward to enable the ripple-carry output (RCO) to produce a high-level pulse while the count is maximum (15). The clocked carry output (CCO) produces a high-level pulse for a duration equal to that of the low level of the clock when RCO is high and the counter is enabled (ENP and ENT are high); otherwise, CCO is low. CCO does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connecting RCO or CCO of the first counter to ENT of the next counter. However, for very high-speed counting, RCO should be used for cascading because CCO does not become active until the clock returns to the low level. The SN54ALS561A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS561A is characterized for operation from 0°C to 70°C.
Part # Description Stock Price
SN74ALS561ADWE4
DISTI # SN74ALS561ADWE4-ND
IC COUNTER BIN 4BIT SYNCH 20SOIC
RoHS: Compliant
Min Qty: 150
Container: Tube
Limited Supply - Call
    SN74ALS561ADWE4
    DISTI # 595-SN74ALS561ADWE4
    Counter ICs Sync 4-Bit Binary Counter W/3-St Otpt
    RoHS: Compliant
    0
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      Availability
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      Available
      On Order:
      4000
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      Due to semiconductor in short supply from 2021,below price is the Normal price before 2021.please send inquire to confirm.
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