TSB81BA3IPFPEP

TSB81BA3IPFPEP
Mfr. #:
TSB81BA3IPFPEP
Description:
1394 Interface IC Mil Enh 3-Port Cable Xcvr/Arbiter
Lifecycle:
New from this manufacturer.
Datasheet:
TSB81BA3IPFPEP Datasheet
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
More Information:
TSB81BA3IPFPEP more Information TSB81BA3IPFPEP Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
1394 Interface IC
RoHS:
Y
Mounting Style:
SMD/SMT
Package / Case:
HTQFP-80
Series:
TSB81BA3-EP
Operating Supply Voltage:
1.85 V to 2.05 V, 3 V to 3.6 V
Minimum Operating Temperature:
- 40 C
Maximum Operating Temperature:
+ 85 C
Packaging:
Tray
Description/Function:
ENHANCED PRODUCT IEEE1394B 3-PORT CABLE TRANSCEIVER/ARBITER
Brand:
Texas Instruments
Moisture Sensitive:
Yes
Product Type:
1394 Interface IC
Factory Pack Quantity:
96
Subcategory:
Interface ICs
Part # Aliases:
V62/04612-01XE
Unit Weight:
0.012984 oz
Tags
TSB81BA3IP, TSB81BA3I, TSB81B, TSB81, TSB8, TSB
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: info@omo-ic.com

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***as Instruments
Enhanced product IEEE 1394b 3-port cable transceiver/arbiter 80-HTQFP -40 to 85
***ical
Transceiver 1TX 1RX 800Mbps 80-Pin HTQFP EP Tray
***ser
IEEE1394 (Firewire) Mil Enh 3-Port Cable Xcvr/Arbiter
***ark
IC, CABLE TXRX/ARBITER, 800MBPS, HTQFP80
***i-Key
IC TRANSCEIVER HALF 6/6 80HTQFP
***AS INSTRUMEN
The TSB81BA3 provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB81BA3 is designed to interface with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. It may also be connected cable port to cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2.
***as Instruments Inc.
The TSB81BA3 is powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The core voltage supply is supplied to the PLLVDD-CORE and DVDD-CORE terminals to the requirements in the recommended operating conditions. The PLLVDD-CORE terminals must be separated from the DVDD-CORE terminals, the PLLVDD-CORE terminals are decoupled with 1 µF and smaller decoupling capacitors, and the DVDD-CORE terminals separately decoupled with a 1 µF and smaller decoupling capacitors. The separation between DVDD-CORE and PLLVDD-CORE may be implemented by separate power supply rails, or by a single power supply rail, where the DVDD-CORE and PLLVDD-CORE are separated by a filter network to keep noise from the PLLVDD-CORE supply.
***AS INSTRUMEN
The TSB81BA3 requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two devices and is used for resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE 1394a-2000 standard. A 98.304-MHz clock signal is supplied to the associated LLC for synchronization of the two devices when operating the PHY-link interface in compliance with the IEEE P1394b standard. The power down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.
***as Instruments Inc.
Data bits to be transmitted through the cable ports are received from the LLC on 2, 4, or 8 parallel paths (depending on the requested transmission speed and PHY-link interface mode of operation). They are latched internally, combined serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbits/s (referred to as S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information stream.
***as Instruments Inc.
The PHY-link interface can follow either the IEEE 1394a-2000 protocol or the IEEE 1394b-2002 protocol. When using a 1394a-2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link interface then operates in accordance with the legacy 1394a-2000 standard. When using a 1394b LLC such as the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the P1394b standard.
***AS INTRUMENTS
The cable interface can follow either the IEEE 1394a-2000 protocol or the 1394b protocol on all ports. The mode of operation is determined by the interface capabilities of the ports being connected. When any of the three ports is connected to a 1394a-2000 compliant device, the cable interface on that port operates in the 1394a-2000 data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a 1394b compliant node, the cable interface on that port operates per the P1394b standard at S400B or S800 speed. The TSB81BA3 automatically determines the correct cable interface connection method for the bilingual ports.
***AS USD
NOTE:The BMODE terminal does not select the cable interface mode of operation. The BMODE terminal selects the PHY-link interface mode of operation and affects the arbitration modes on the cable. When the BMODE terminal is deasserted, BOSS arbitration is disabled.
***ASIN
During packet reception the serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected and active cable ports.
***XS
Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration when connected to a 1394a-2000 compliant device. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during 1394a-mode arbitration and sets the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted pair bias (TPBIAS) voltage.
***AS INSRUMENT
When connected to a 1394a-2000 compliant node, the TSB81BA3 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits (one for each port). This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF.
***as Instr.
The line drivers in the TSB81BA3, are designed to work with external 112- and 270 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. A precision external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents.
***AS INTRUMENTS
When the power supply of the TSB81BA3 is off while the twisted-pair cables are connected, the TSB81BA3 transmitter and receiver circuitry present a high-impedance signal to the cable that does not load the device at the other end of the cable.
***AS INST
When the TSB81BA3 is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the port must be forced to the 1394a-only mode (Data-Strobe-only mode), then the TPB+ and TPB- terminals can be tied together and then pulled to ground; or the TPB+ and TPB- terminals can be connected to the suggested normal termination network. The TPA+ and TPA- terminals of an unused port can be left unconnected. The TPBIAS terminal can be connected to a 1-µF capacitor to ground or left unconnected.
***
To operate a port as a 1394b bilingual port, the force data-strobe-only terminal for the port (DS0, DS1, or DS2) needs to be pulled to ground through a 1-k resistor. The only time the port must be forced to the data-strobe-only mode is if the port is connected to a 1394a connector (either 6-pin, which is recommended, or 4-pin). This mode is provided to ensure that 1394b signalling is never sent across a 1394a cable.
***AS INSTRUM
The TESTM, TESTW, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM and TESTW terminals must be connected to VDD through a 1-k resistor.
***
Three package terminals are used as inputs to set the default value for three configuration status bits in the self-ID packet. They may be pulled high through a 1-k resistor or hardwired low as a function of the equipment design. The PC0, PC1, and PC2 terminals indicate the default power class status for the node (the need for power from the cable or the ability to supply power to the cable). The contender bit in the PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager (BM). On the TSB81BA3, this bit may only be set by a write to the PHY register set. If a node desires to be a contender for IRM or BM, then the node software must set this bit in the PHY register set.
***AS INSTRU
The LPS (link power status) terminal works with the LKON/DS2 terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit to indicate the active/power status of the LLC. The LPS signal also resets, disables, and initializes the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit).
***XS
The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the TSB81BA3 detects that the LPS input is inactive, the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The TSB81BA3 continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB81BA3 issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the PHY LLC now being accessible).
***AS USD
The PHY uses the LKON/DS2 terminal to notify the LLC to power up and become active. When activated, the output LKON/DS2 signal is a square wave. The PHY activates the LKON/DS2 output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the LKON/DS2 output when the LLC becomes active (both LPS sensed as active and the LCtrl bit set to 1). The PHY also deasserts the LKON/DS2 output when a bus reset occurs, unless a PHY interrupt condition exists which would otherwise cause LKON/DS2 to be active. If the PHY is power cycled and the power class is 0 through 4, then the PHY asserts LKON/DS2 for approximately 167 µs or until both the LPS is active and the LCtrl bit is 1.
RF Transceiver sub 1GHZ list
Close Close
Part # Description Stock Price
TSB81BA3IPFPEP
DISTI # 29460154
Transceiver 1TX 1RX 800Mbps 80-Pin HTQFP EP Tray
RoHS: Compliant
2112
  • 1000:$13.0410
  • 500:$13.2210
  • 100:$13.5810
  • 96:$14.1210
TSB81BA3IPFPEP
DISTI # 296-22530-ND
IC TXRX CABLE 3 PORT 80HTQFP
RoHS: Compliant
Min Qty: 96
Container: Tray
Temporarily Out of Stock
  • 96:$18.1300
TSB81BA3IPFPEP
DISTI # TSB81BA3IPFPEP
Transceiver 1TX 1RX 800Mbps 80-Pin HTQFP EP Tray - Trays (Alt: TSB81BA3IPFPEP)
RoHS: Compliant
Min Qty: 1
Container: Tray
Americas - 9
  • 1:$19.8900
  • 10:$18.2900
  • 25:$17.3900
  • 50:$17.2900
  • 100:$14.9900
  • 500:$13.7900
  • 1000:$13.6900
TSB81BA3IPFPEP
DISTI # 595-TSB81BA3IPFPEP
1394 Interface IC Mil Enh 3-Port Cable Xcvr/Arbiter
RoHS: Compliant
60
  • 1:$20.5700
  • 10:$18.9100
  • 25:$17.9300
  • 100:$15.9700
  • 250:$15.1900
  • 500:$14.2100
V62/04612-01XE
DISTI # 595-V62/04612-01XE
1394 Interface IC Mil Enh 3-Port Cable Xcvr/Arbiter
RoHS: Compliant
0
    TSB81BA3IPFPEP 
    RoHS: Compliant
    Europe - 96
      Image Part # Description
      LTC2379IDE-18#PBF

      Mfr.#: LTC2379IDE-18#PBF

      OMO.#: OMO-LTC2379IDE-18-PBF

      Analog to Digital Converters - ADC 18-Bit, 1.6Msps, 101dB SNR, Low Power SAR ADC with Serial Interface
      INA220AIDGST

      Mfr.#: INA220AIDGST

      OMO.#: OMO-INA220AIDGST

      Current & Power Monitors & Regulators Bi-Direct Current Power Monitor
      ESD204DQAR

      Mfr.#: ESD204DQAR

      OMO.#: OMO-ESD204DQAR

      TVS Diodes / ESD Suppressors 4-Channel Low-Capacitance Surge and ESD Protection Diode 10-USON -40 to 125
      SN74F157AD

      Mfr.#: SN74F157AD

      OMO.#: OMO-SN74F157AD

      Encoders, Decoders, Multiplexers & Demultiplexers Quad 2 to 1
      MT46V32M16P-5B IT:J

      Mfr.#: MT46V32M16P-5B IT:J

      OMO.#: OMO-MT46V32M16P-5B-IT-J

      DRAM DDR 512M 32MX16 TSOP
      PI2DBS6212ZHEX

      Mfr.#: PI2DBS6212ZHEX

      OMO.#: OMO-PI2DBS6212ZHEX

      Multiplexer Switch ICs 6.5Gbps Broadband Differential
      INA220AIDGST

      Mfr.#: INA220AIDGST

      OMO.#: OMO-INA220AIDGST-TEXAS-INSTRUMENTS

      IC CURRENT MONITOR 1% 10MSOP
      T491C107K006AT

      Mfr.#: T491C107K006AT

      OMO.#: OMO-T491C107K006AT-KEMET

      Tantalum Capacitors - Solid SMD 6.3volts 100uF 10% C
      TSB82AA2PGE

      Mfr.#: TSB82AA2PGE

      OMO.#: OMO-TSB82AA2PGE-TEXAS-INSTRUMENTS

      1394 Interface IC OHCI-Lynx Controlle
      SN74F157AD

      Mfr.#: SN74F157AD

      OMO.#: OMO-SN74F157AD-TEXAS-INSTRUMENTS

      Encoders, Decoders, Multiplexers & Demultiplexers Quad 2 to 1
      Availability
      Stock:
      95
      On Order:
      2078
      Enter Quantity:
      Current price of TSB81BA3IPFPEP is for reference only, if you want to get best price, please submit a inquiry or direct email to our sales team sales@omo-ic.com
      Reference price (USD)
      Quantity
      Unit Price
      Ext. Price
      1
      $20.32
      $20.32
      10
      $18.68
      $186.80
      25
      $17.71
      $442.75
      100
      $15.77
      $1 577.00
      250
      $15.00
      $3 750.00
      500
      $14.03
      $7 015.00
      Due to semiconductor in short supply from 2021,below price is the Normal price before 2021.please send inquire to confirm.
      Start with
      Newest Products
      Top