CDC857-3DGGG4

CDC857-3DGGG4
Mfr. #:
CDC857-3DGGG4
Description:
Phase Locked Loops - PLL Phase-Lock Loop Clock Drivers
Lifecycle:
New from this manufacturer.
Datasheet:
CDC857-3DGGG4 Datasheet
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
More Information:
CDC857-3DGGG4 more Information CDC857-3DGGG4 Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Phase Locked Loops - PLL
RoHS:
Y
Type:
PLL Clock Driver
Number of Circuits:
1
Supply Voltage - Max:
3.6 V
Supply Voltage - Min:
3 V
Minimum Operating Temperature:
0 C
Maximum Operating Temperature:
+ 85 C
Mounting Style:
SMD/SMT
Package / Case:
TSSOP-48
Packaging:
Tube
Height:
1.15 mm
Length:
12.5 mm
Width:
6.1 mm
Brand:
Texas Instruments
Operating Supply Voltage:
3.3 V
Product Type:
PLLs - Phase Locked Loops
Factory Pack Quantity:
1
Subcategory:
Wireless & RF Integrated Circuits
Unit Weight:
0.014850 oz
Tags
CDC857-3, CDC85, CDC8, CDC
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC 3.3V PLL CLK-DRVR 48-TSSOP
***ark
IC, PLL CLOCK DRIVER, 167MHZ, TSSOP-48; Clock IC Type:PLL Clock Driver; Frequency:167MHz; No. of Outputs:10; Supply Current:235mA; Supply Voltage Range:3V to 3.6V; Digital IC Case Style:TSSOP; No. of Pins:48 ;RoHS Compliant: Yes
***as Instruments
The CDC857-2 and CDC857-3 are high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The CDC857-3 operates at 3.3 V (PLL) and 2.5 V (output buffer). The CDC857-2 operates at 2.5 V (PLL and output buffer). One bank of ten inverting and noninverting outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance state (3-state). Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. If AVCC is at GND and VCC = ON, 2 falling edges on G cause the PLL to run with FBOUT being enabled and all other outputs being disabled, after AVCC ramps up to its specified VCC value, with G being kept low. The CDC857 is characterized for operation from 0C to 85C.
Part # Description Stock Price
CDC857-3DGGG4
DISTI # CDC857-3DGGG4-ND
IC 3.3V PLL CLK-DRVR 48-TSSOP
RoHS: Compliant
Min Qty: 80
Container: Tube
Limited Supply - Call
    CDC857-3DGGG4
    DISTI # 595-CDC857-3DGGG4
    Phase Locked Loops - PLL Phase-Lock Loop Clock Drivers
    RoHS: Compliant
    0
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      OMO.#: OMO-CDC857-2DGGRG4

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      Availability
      Stock:
      Available
      On Order:
      2500
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