SN74V293-7PZA

Mfr. #:: SN74V293-7PZA
Description:: FIFO 65536 x 18 Synch FIFO Memory
Lifecycle:: New from this manufacturer.
Datasheet:: SN74V293-7PZA Datasheet
Delivery:: DHL FedEx Ups TNT EMS
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ECAD Model:
More Information:: SN74V293-7PZA more Information SN74V293-7PZA Product Details

Product Attribute
Attribute Value

Manufacturer:: Texas Instruments

Product Category:: FIFO

RoHS:: Y

Data Bus Width:: 9 bit, 18 bit

Bus Direction:: Unidirectional

Memory Size:: 1.125 Mbit

Timing Type:: Synchronous

Organization:: 128 k x 9, 64 k x 18

Number of Circuits:: 2

Maximum Clock Frequency:: 133 MHz

Access Time:: 5 ns

Supply Voltage - Max:: 3.45 V

Supply Voltage - Min:: 3.15 V

Supply Current - Max:: 35 mA

Minimum Operating Temperature:: 0 C

Maximum Operating Temperature:: + 70 C

Package / Case:: LQFP-80

Packaging:: Tray

Height:: 1.4 mm

Series:: SN74V293

Width:: 14 mm

Brand:: Texas Instruments

Mounting Style:: SMD/SMT

Moisture Sensitive:: Yes

Operating Supply Voltage:: 3.3 V

Product Type:: FIFO

Factory Pack Quantity:: 90

Subcategory:: Memory & Data Storage

Unit Weight:: 0.022575 oz

Tags: SN74V29, SN74V2, SN74V, SN74, SN7

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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74V293-7PZA Ratings and Reviews

A***v

Everything is fine. thank you very much! but very, very long delivery.

2019-04-17

A***a

Thank you!

2019-04-13

D***a

good

2019-05-13

SN74V293-7PZA Description

***roFlash: FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18/128K x 9 80-Pin LQFP Tray

***as Instruments: 65536 x 18 Synchronous FIFO Memory 80-LQFP 0 to 70

***AS INSTR: The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow.

***as Instruments Inc.: There is flexible ×9/×18 bus matching on both read and write ports.

***AS: The period required by the retransmit operation is fixed and short.

***AS INSTRUM: The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short.

***AS INSTR: These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes.

***: Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit or 9-bit width, as determined by the state of external control pins input width (IW) and output width (OW) during the master-reset cycle.

***AS INS: The input port is controlled by write-clock (WCLK) and write-enable (WEN)\ inputs. Data is written into the FIFO on every rising edge of WCLK when WEN\ is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN)\ inputs. Data is read from the FIFO on every rising edge of RCLK when REN\ is asserted. An output-enable (OE)\ input is provided for 3-state control of the outputs.

***AS INSTRUMEN: The frequencies of both the RCLK and the WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other.

***OMO Electronic: There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode.

***AS INSRUMENT: In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN\ need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN\ for access. The state of the FWFT/SI input during master reset determines the timing mode in use.

***ASIN: In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines.

***TEXAS: For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required.

***AS INSTUMENTS: These FIFOs have five flag pins: empty flag or output ready (EF\/OR\), full flag or input ready (FF\/IR\), half-full flag (HF)\, programmable almost-empty flag (PAE)\, and programmable almost-full flag (PAF)\. The IR\ and OR\ functions are selected in FWFT mode. The EF\ and FF\ functions are selected in standard mode. HF\, PAE\, and PAF\ always are available for use, regardless of timing mode.

***AS INSTR: PAE\ and PAF\ can be programmed independently to switch at any point in memory. Programmable offsets determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset settings also are provided, so that PAE\ can be set to switch at a predefined number of locations from the empty boundary. The PAF\ threshold also can be set at similar predefined values from the full boundary. The default offset values are set during master reset by the state of FSEL0, FSEL1, and LD\.

***as Instruments (TI): For serial programming, SEN\, together with LD\, loads the offset registers via the serial input (SI) on each rising edge of WCLK. For parallel programming, WEN\, together with LD\, loads the offset registers via Dn on each rising edge of WCLK. REN\, together with LD\, can read the offsets in parallel from Qn on each rising edge of RCLK, regardless of whether serial or parallel offset loading has been selected.

***ASIN: Also, the timing modes of PAE\ and PAF\ outputs can be selected. Timing modes can be set to be either asynchronous or synchronous for PAE\ and PAF\.

***AS: If the asynchronous PAE\/PAF\ configuration is selected, PAE\ is asserted low on the low-to-high transition of RCLK. PAE\ is reset to high on the low-to-high transition of WCLK. Similarly, PAF\ is asserted low on the low-to-high transition of WCLK, and PAF\ is reset to high on the low-to-high transition of RCLK.

***XS: If the synchronous PAE\/PAF\ configuration is selected , PAE\ is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF\ is asserted and updated on the rising edge of WCLK only and not RCLK. The desired mode is configured during master reset by the state of the programmable-flag mode (PFM) pin.

***AS INSTRUM: The retransmit function allows data to be reread from the FIFO more than once. A low on the RT\ input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode (RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency.

***XS: If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register with respect to the same RCLK edge that initiated the retransmit, if RT\ is low.

***AS USD: During master reset (MRS)\, the functions for all the operating modes are programmed. These include FWFT or standard timing, input bus width, output bus width, big endian or little endian, retransmit mode, programmable-flag operating and programming method, programmable-flag default offsets, and interspersed parity select. The read and write pointers are set to the first location of the FIFO. Then, based on the selected timing mode, EF\ is set low or OR\ is set high and FF\ is set high or IR\ is set low. Also, PAE\ is set low, PAF\ is set high, and HF\ is set high. The Q outputs are set low.

***AS INSTR: Partial reset (PRS)\ also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable-flag programming method, default or programmed offset settings, input and output bus widths, big endian/little endian, interspersed parity select, and retransmit mode existing before partial reset is asserted remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS\ is useful for resetting a device in mid-operation when reprogramming programmable flags and other functions would be undesirable.

***AS INSTRUMENTS INC: A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO in long-word (×18) format and read out of the FIFO in small-word (×9) format. If big-endian mode is selected, the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed by the least significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state of the big-endian/little-endian (BE)\ pin.

***AS INSTRUMENT: The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is located in bit position D8 during the parallel programming of the flag offsets. If noninterspersed-parity mode is selected, D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during master reset by the state of the IP input pin. This mode is relevant only when the input width is set to ×18 mode.

***AS INSTR: The SN74V263, SN74V273, SN74V283, and SN74V293 are fabricated using TIs high-speed submicron CMOS technology.

***AS INS: For more information on this device family, see the following application reports:

Market price

Part #	Description	Stock	Price
SN74V293-7PZA DISTI # V39:1801_07360563	FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18/128K x 9 80-Pin LQFP Tray RoHS: Compliant	0
SN74V293-7PZA DISTI # 296-12492-ND	IC SYNC FIFO MEM 65536X18 80LQFP RoHS: Compliant Min Qty: 1 Container: Tray	124In Stock	180:$35.0906 90:$38.7207 10:$40.4150 1:$43.3200
SN74V293-7PZA DISTI # SN74V293-7PZA	FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18/128K x 9 80-Pin LQFP (Alt: SN74V293-7PZA) RoHS: Compliant Min Qty: 90	Europe - 63	900:€27.9900 540:€29.1900 360:€30.3900 180:€33.3900 90:€36.9900
SN74V293-7PZA DISTI # SN74V293-7PZA	FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18/128K x 9 80-Pin LQFP - Trays (Alt: SN74V293-7PZA) RoHS: Not Compliant Min Qty: 90 Container: Tray	Americas - 0	900:$27.7687 540:$28.4543 360:$29.1747 180:$29.9325 90:$30.3263
SN74V293-7PZA	65536 x 18 Synchronous FIFO Memory	3600	1000:$26.1900 750:$26.2800 500:$29.2700 250:$31.1200 100:$31.3500 25:$35.2600 10:$36.4200 1:$38.9500
SN74V293-7PZA DISTI # 595-SN74V293-7PZA	FIFO 65536 x 18 Synch FIFO Memory RoHS: Compliant	278	1:$41.2500 5:$40.3400 10:$38.5000 25:$36.8800 100:$33.4200
SN74V293-7PZA	FIFO, 64KX18, 5ns, Synchronous, CMOS, PQFP80 RoHS: Compliant	760	1000:$30.3300 500:$31.9300 100:$33.2400 25:$34.6600 1:$37.3300
SN74V293-7PZA DISTI # 6625377P	FIFO MEM SYNC DUAL DEPTH/WIDTH UNI-DIR, PU	228	45:£34.2800 18:£35.5300

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