CD4029BPWE4

CD4029BPWE4
Mfr. #:
CD4029BPWE4
Description:
Counter ICs CMOS Presettable Up/Down Counter
Lifecycle:
New from this manufacturer.
Datasheet:
CD4029BPWE4 Datasheet
Delivery:
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ECAD Model:
More Information:
CD4029BPWE4 more Information CD4029BPWE4 Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Counter ICs
RoHS:
Y
Mounting Style:
SMD/SMT
Package / Case:
TSSOP-16
Logic Family:
CMOS
Counting Method:
Asynchronous
Counting Sequence:
Up/Down
Operating Supply Voltage:
3 V to 18 V
Minimum Operating Temperature:
- 55 C
Maximum Operating Temperature:
+ 125 C
Packaging:
Tube
Operating Temperature Range:
- 55 C to + 125 C
Brand:
Texas Instruments
Product Type:
Counter ICs
Factory Pack Quantity:
1
Subcategory:
Counter ICs
Unit Weight:
0.006102 oz
Tags
CD4029BP, CD4029B, CD4029, CD402, CD40, CD4
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***ser
Counter ICs CMOS Presettable Up/Down Counter
***ark
Counter Logic IC; Logic Family:CD4000; Supply Voltage Min:3V; Supply Voltage Max:18V; Package/Case:16-TSSOP; No. of Pins:16; Operating Temperature Range:-55°C to +125°C; Input Type:CMOS; Leaded Process Compatible:Yes ;RoHS Compliant: Yes
***as Instruments
CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN\ (CLOCK ENABLE\), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT\ signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN\ and PRESET ENALBE signals are low. Advancement is inhibited when the CARRY-IN\ or PRESET ENABLE signals are high. The CARRY-OUT\ signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN\ signal is low. The CARRY-IN\ signal in the low state can thus be considered a CLOCK ENABLE\. The CARRY-IN\ terminal must be connected to VSS when not in use. Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Multiple packages can be connected in either a parallel-clocking or a ripple-clocking arrangement as shown in Fig. 17. Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times. The CD4029B-series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
Part # Description Stock Price
CD4029BPWE4
DISTI # CD4029BPWE4-ND
IC PRESET UP/DWN COUNTER 16TSSOP
RoHS: Compliant
Min Qty: 2160
Container: Tube
Limited Supply - Call
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    Availability
    Stock:
    Available
    On Order:
    3500
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