Chapter 1: Cyclone III Device Family Overview 1–7
Cyclone III Device Family Architecture
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 1
Memory Blocks
Each M9K memory block of the Cyclone III device family provides nine Kbits of
on-chip memory capable of operating at up to 315 MHz for Cyclone III devices and up
to 274 MHz for Cyclone III LS devices. The embedded memory structure consists of
M9K memory blocks columns that you can configure as RAM, first-in first-out (FIFO)
buffers, or ROM. The Cyclone III device family memory blocks are optimized for
applications such as high throughout packet processing, embedded processor
program, and embedded data storage.
The Quartus II software allows you to take advantage of the M9K memory blocks by
instantiating memory using a dedicated megafunction wizard or by inferring memory
directly from the VHDL or Verilog source code.
M9K memory blocks support single-port, simple dual-port, and true dual-port
operation modes. Single-port mode and simple dual-port mode are supported for all
port widths with a configuration of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36. True
dual-port is supported in port widths with a configuration of ×1, ×2, ×4, ×8, ×9, ×16,
and ×18.
f For more information about memory blocks, refer to the Memory Blocks in the Cyclone
III Device Family chapter.
Embedded Multipliers and Digital Signal Processing Support
Cyclone III devices support up to 288 embedded multiplier blocks and Cyclone III LS
devices support up to 396 embedded multiplier blocks. Each block supports one
individual 18 × 18-bit multiplier or two individual 9 × 9-bit multipliers.
The Quartus II software includes megafunctions that are used to control the operation
mode of the embedded multiplier blocks based on user parameter settings.
Multipliers can also be inferred directly from the VHDL or Verilog source code. In
addition to embedded multipliers, Cyclone III device family includes a combination
of on-chip resources and external interfaces, making them ideal for increasing
performance, reducing system cost, and lowering the power consumption of digital
signal processing (DSP) systems. You can use Cyclone III device family alone or as
DSP device co-processors to improve price-to-performance ratios of DSP systems.
The Cyclone III device family DSP system design support includes the following
features:
DSP IP cores:
Common DSP processing functions such as finite impulse response (FIR), fast
Fourier transform (FFT), and numerically controlled oscillator (NCO) functions
Suites of common video and image processing functions
Complete reference designs for end-market applications
DSP Builder interface tool between the Quartus II software and the MathWorks
Simulink and MATLAB design environments
DSP development kits
f For more information about embedded multipliers and digital signal processing
support, refer to the Embedded Multipliers in Cyclone III Devices chapter.
1–8 Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Architecture
Cyclone III Device Handbook July 2012 Altera Corporation
Volume 1
Clock Networks and PLLs
Cyclone III device family includes 20 global clock networks. You can drive global
clock signals from dedicated clock pins, dual-purpose clock pins, user logic, and
PLLs. Cyclone III device family includes up to four PLLs with five outputs per PLL to
provide robust clock management and synthesis. You can use PLLs for device clock
management, external system clock management, and I/O interfaces.
You can dynamically reconfigure the Cyclone III device family PLLs to enable
auto-calibration of external memory interfaces while the device is in operation. This
feature enables the support of multiple input source frequencies and corresponding
multiplication, division, and phase shift requirements. PLLs in Cyclone III device
family may be cascaded to generate up to ten internal clocks and two external clocks
on output pins from a single external clock source.
f For more PLL specifications and information, refer to the Cyclone III Device Data Sheet,
Cyclone III LS Device Data Sheet, and Clock Networks and PLLs in the Cyclone III Device
Family chapters.
I/O Features
Cyclone III device family has eight I/O banks. All I/O banks support single-ended
and differential I/O standards listed in Table 16.
The Cyclone III device family I/O also supports programmable bus hold,
programmable pull-up resistors, programmable delay, programmable drive strength,
programmable slew-rate control to optimize signal integrity, and hot socketing.
Cyclone III device family supports calibrated on-chip series termination (R
S
OCT) or
driver impedance matching (Rs) for single-ended I/O standards, with one OCT
calibration block per side.
f For more information, refer to the I/O Features in the Cyclone III Device Family chapter.
High-Speed Differential Interfaces
Cyclone III device family supports high-speed differential interfaces such as BLVDS,
LVDS, mini-LVDS, RSDS, and PPDS. These high-speed I/O standards in Cyclone III
device family provide high data throughput using a relatively small number of I/O
pins and are ideal for low-cost applications. Dedicated differential output drivers on
the left and right I/O banks can send data rates at up to 875 Mbps for Cyclone III
devices and up to 740 Mbps for Cyclone III LS devices, without the need for external
resistors. This saves board space or simplifies PCB routing. Top and bottom I/O banks
support differential transmission (with the addition of an external resistor network)
data rates at up to 640 Mbps for both Cyclone III and Cyclone III LS devices.
Table 1–6. Cyclone III Device Family I/O Standards Support
Type I/O Standard
Single-Ended I/O LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X
Differential I/O SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDS
Chapter 1: Cyclone III Device Family Overview 1–9
Cyclone III Device Family Architecture
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 1
f For more information, refer to the High-Speed Differential Interfaces in the Cyclone III
Device Family chapter.
Auto-Calibrating External Memory Interfaces
Cyclone III device family supports common memory types such as DDR, DDR2,
SDR SDRAM, and QDRII SRAM. DDR2 SDRAM memory interfaces support data
rates up to 400 Mbps for Cyclone III devices and 333 Mbps for Cyclone III LS devices.
Memory interfaces are supported on all sides of Cyclone III device family. Cyclone III
device family has the OCT, DDR output registers, and 8-to-36-bit programmable DQ
group widths features to enable rapid and robust implementation of different
memory standards.
An auto-calibrating megafunction is available in the Quartus II software for DDR and
QDR memory interface PHYs. This megafunction is optimized to take advantage of
the Cyclone III device family I/O structure, simplify timing closure requirements, and
take advantage of the Cyclone III device family PLL dynamic reconfiguration feature
to calibrate PVT changes.
f For more information, refer to the External Memory Interfaces in the Cyclone III Device
Family chapter.
Support for Industry-Standard Embedded Processors
To quickly and easily create system-level designs using Cyclone III device family, you
can select among the ×32-bit soft processor cores: Freescale
®
V1 Coldfire, ARM
®
Cortex M1, or Altera Nios
®
II, along with a library of 50 other IP blocks when using
the system-on-a-programmable-chip (SOPC) Builder tool. SOPC Builder is an Altera
Quartus II design tool that facilitates system-integration of IP blocks in an FPGA
design. The SOPC Builder automatically generates interconnect logic and creates a
testbench to verify functionality, saving valuable design time.
Cyclone III device family expands the peripheral set, memory, I/O, or performance of
legacy embedded processors. Single or multiple Nios II embedded processors are
designed into Cyclone III device family to provide additional co-processing power, or
even replace legacy embedded processors in your system. Using the Cyclone III
device family and Nios II together provide low-cost, high-performance embedded
processing solutions, which in turn allow you to extend the life cycle of your product
and improve time-to-market over standard product solutions.
1 Separate licensing of the Freescale and ARM embedded processors are required.
Hot Socketing and Power-On-Reset
Cyclone III device family features hot socketing (also known as hot plug-in or hot
swap) and power sequencing support without the use of external devices. You can
insert or remove a board populated with one or more Cyclone III device family
during a system operation without causing undesirable effects to the running system
bus or the board that was inserted into the system.

EP3C16F256C6

Mfr. #:
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array FPGA - Cyclone III 963 LABs 168 IOs
Lifecycle:
New from this manufacturer.
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