©2014 Silicon Storage Technology, Inc. DS20005053B 04/14
23
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Figure 12:WE# Controlled Block-Erase Timing Diagram
Figure 13:WE# Controlled Sector-Erase Timing Diagram
25053 F32.0
ADDRESSES
DQ
15-0
WE#
555 2AA 2AA555 555
XX55
XX30
XX55XXAA
XX80
XXAA
BA
X
OE#
CE#
RY/BY#
VALID
SIX-BYTE CODE FOR BLOCK-ERASE
T
WP
T
BE
T
BY
T
BR
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are inter-
changeable as long as minimum timings are met. (See Table 18).
BA
X
= Block Address
WP# must be held in proper logic state (V
IL
or V
IH
) 1µs prior to and 1µs after the command sequence.
X can be V
IL
or V
IH
, but no other value.
25053 F28.0
ADDRESSES
DQ
15-0
WE#
555 2AA 2AA555 555
XX55
XX50
XX55XXAA
XX80
XXAA
SA
X
OE#
CE#
RY/BY#
VALID
SIX-BYTE CODE FOR SECTOR-ERASE
T
WP
T
SE
T
BY
T
BR
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are inter-
changeable as long as minimum timings are met. (See Table 18).
SA
X
= Block Address
WP# must be held in proper logic state (V
IL
or V
IH
) 1µs prior to and 1µs after the command sequence.
X can be V
IL
or V
IH
, but no other value.
