SST39VF401C-70-4C-MAQE

low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever

occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

The SST39VF401C/402C and SST39LF401C/402C also have the Auto Low Power mode which puts

reduces the I

reduces the typical I

exits the Auto Low Power mode with any address transition or control signal transition used to initiate

another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power

mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high.

When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output con-

trol and is used to gate data from the output pins. The data bus is in high impedance state when either

CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6).

The SST39VF401C/402C and SST39LF401C/402C are programmed on a word-by-word basis. Before

programming, the sector where the word exists must be fully erased. The Program operation is accom-

plished in three steps. The first step is the three-byte load sequence for Software Data Protection. The

second step is to load word address and word data. During the Word-Program operation, the

addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is

latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal

Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs

first. The Program operation, once initiated, will be completed within 10 µs. See Figures 7 and 8 for

WE# and CE# controlled Program operation timing diagrams and Figure 22 for flowchar ts. During the

Block-Erase mode.

The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based

on non-uniform block sizes—seven 32 KWord, one 16 KWord, two 4 KWord, and one 8 KWord blocks.

See Figure 2 for top and bottom boot device block addresses. The Sector-Erase operation is initiated

by executing a six-byte command sequence with Sector-Erase command (50H) and sector address

(SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command

sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector

or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or

50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the

sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle

data to be read from any memory location, or program data into any sector/block that is not suspended

for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-

Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the

Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not

suspended from an Erase operation. Reading at address location within erase-suspended sectors/

blocks will output DQ

tion is allowed except for the sector or block selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue

Erase Resume command. The operation is executed by issuing one byte command sequence with

command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising

edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is

Toggle Bit or Data# Polling. See Table 7 for the command sequence, Figure 11 for timing diagram, and

Figure 26 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When

WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should

be statically held high or low.

The SST39VF401C/402C and SST39LF401C/402C provide two software means to detect the comple-

tion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software

detection includes two status bits: Data# Polling (DQ

either DQ

routine should include a loop to read the accessed location an additional two (2) times. If both reads

are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that

indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain out-

put, it allows several devices to be tied in parallel to V

edge of the final WE# pulse in the command sequence, the RY/BY# status is valid.

completed, DQ

ing the completion of an internal Write operation, the remaining data outputs may still be inv alid: valid data on

the entire data bus will appear in subsequent successiv e Read cycles after an interv al of 1 µs. During internal

Erase operation, any attempt to read DQ

pleted, DQ

pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the ris-

, Block-, or Chip-Erase, the toggle bit (DQ

DQ

gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ