XCR3256XL-12TQ144C

XCR3256XL 256 Macrocell CPLD
4 www.xilinx.com DS013 (v2.7) March 31, 2006
Product Specification
R
Internal Timing Parameters
(1,2)
Symbol Parameter
-7 -10 -12
UnitMin. Max. Min. Max. Min. Max.
Buffer Delays
T
IN
Input buffer delay - 2.5 - 3.3 - 4.0 ns
T
FIN
Fast input buffer delay - 2.7 - 3.3 - 3.3 ns
T
GCK
Global clock buffer delay - 1.0 - 1.3 - 1.5 ns
T
OUT
Output buffer delay - 2.5 - 3.2 - 3.8 ns
T
EN
Output buffer enable/disable delay - 4.5 - 5.2 - 6.0 ns
Internal Register and Combinatorial Delays
T
LDI
Latch transparent delay - 1.3 - 1.6 - 2.0 ns
T
SUI
Register setup time 0.8 - 1.0 - 1.2 - ns
T
HI
Register hold time 0.3 - 0.5 - 0.7 - ns
T
ECSU
Register clock enable setup time 2.0 - 2.5 - 3.0 - ns
T
ECHO
Register clock enable hold time 3.0 - 4.5 - 5.5 - ns
T
COI
Register clock to output delay - 1.0 - 1.3 - 1.6 ns
T
AOI
Register async. S/R to output delay - 2.0 - 2.0 - 2.2 ns
T
RAI
Register async. recovery - 5.0 - 7.0 - 8.0 ns
T
PTCK
Product term clock delay - 2.0 - 2.5 - 3.0 ns
T
LOGI1
Internal logic delay (single p-term) - 2.0 - 2.5 - 3.0 ns
T
LOGI2
Internal logic delay (PLA OR term) - 2.5 - 3.5 - 4.2 ns
Feedback Delays
T
F
ZIA delay - 2.2 - 3.7 - 4.4 ns
Time Adders
T
LOGI3
Fold-back NAND delay - 2.0 - 2.5 - 3.0 ns
T
UDA
Universal delay - 2.0 - 2.5 - 3.0 ns
T
SLEW
Slew rate limited delay - 4.0 - 5.0 - 6.0 ns
Notes:
1. These parameters guaranteed by design and/or characterization, not testing.
2. See the CoolRunner XPLA3 family data sheet (
DS012) for the timing model.
XCR3256XL 256 Macrocell CPLD
DS013 (v2.7) March 31, 2006 www.xilinx.com 5
Product Specification
R
Switching Characteristics
Figure 3: AC Load Circuit
V
CC
V
OUT
V
IN
C1
R1
R2
S1
S2
DS013_03_102401
Component Values
R1 390Ω
R2 390Ω
C1 35 pF
Measurement S1 S2
T
POE
(High)
T
POE
(Low)
T
P
Open Closed
Closed Open
Closed
Closed
Note: For T
POD
, C1 = 5 pF. Delay measured at
output level of V
OL
+ 300 mV, V
OH
– 300 mV.
Figure 4: Derating Curve for T
PD2
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.0
6.1
6.2
6.3
6.4
6.5
124816
DS013_04_042800
Number of Adjacent Outputs Switching
(ns)
Figure 5: Voltage Waveform
90%
10%
1.5 ns 1.5 ns
DS017_05_042800
+3.0V
0V
Measurements:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
T
R
T
L
XCR3256XL 256 Macrocell CPLD
6 www.xilinx.com DS013 (v2.7) March 31, 2006
Product Specification
R
Pin Descriptions
Table 2: XCR3256XL User I/O Pins
TQ144 PQ208 FT256 CS280
Total User I/O Pins 120 164 164 164
Table 3: XCR3256XL I/O Pins
Function
Block
Macro-
cell TQ144 PQ208 FT256 CS280
1 1 106 6 C16 E18
12-7F12E19
13104
(1)
8D16F15
1 4 103 9 E14 F17
1 5 102 10 E15 F18
16--- -
17--- -
18--- -
19--- -
110--- -
111--- -
11210111F13F19
1 13 100 12 E16 G16
1149913F14G17
1 15 - 15 F15 G19
116-16G12H16
2 1 107 4 E13 B19
2 2 108 3 D15 B18
23-206C13B17
24-205A14A18
2 5 109 204 E11 A17
26--- -
27--- -
28--- -
29--- -
210--- -
211--- -
2 12 110 203 A13 C16
2 13 111 202 D12 A16
2 14 - 201 B13 E15
2 15 112 199 C12 D15
2 16 113 198 A12 A15
3 1 98 17 G15 H17
3 2 97 18 G13 H18
3 3 96 19 F16 H19
3 4 94 20 G14 J16
3 5 93 21 G16 J17
36--- -
37--- -
38--- -
39--- -
310--- -
311--- -
3129222H13J18
3 13 - 24 H12 K16
3149125H15K17
3159026H14K18
316-27H16L16
41114197D11E14
4 2 116 196 A11 D14
43117195E10A14
4 4 - 194 B12 C13
45118193C11B13
46--- -
47--- -
48--- -
49--- -
410--- -
411--- -
412119192B11A13
4 13 120 190 A10 A12
4 14 121 189
(1)
C10
(1)
C12
(1)
4 15 - 188 A9 B12
4 16 122 187 D9 D12
5189
(1)
28 J14 L17
5 2 - 29 J15 L18
5 3 88 30
(1)
J13
(1)
L19
(1)
5 4 87 31 J16 M16
5 5 86 33 L14 M18
Table 3: XCR3256XL I/O Pins (Continued)
Function
Block
Macro-
cell TQ144 PQ208 FT256 CS280

XCR3256XL-12TQ144C

Mfr. #:
Manufacturer:
Xilinx
Description:
CPLD - Complex Programmable Logic Devices XCR3256XL-12TQ144C
Lifecycle:
New from this manufacturer.
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