MAX1288ETA+T Datasheet MAX1288ETA+T, MAX1286EKA+T, MAX1287ETA+T | P10-P12

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

10 ______________________________________________________________________________________

Output Data Format

Figures 5a and 5b illustrate the conversion timing for the

MAX1286–MAX1289. The 12-bit conversion result is out-

put in MSB-first format. Data on DOUT transitions

on the falling edge of SCLK. All 12 bits must be clocked

out before CNVST transitions again. For the MAX1288/

MAX1289, data is straight binary for unipolar mode and

two’s complement for bipolar mode. For the MAX1286/

MAX1287, data is always straight binary.

Transfer Function

Figure 6 shows the unipolar transfer function for the

MAX1286–MAX1289. Figure 7 shows the bipolar transfer

function for the MAX1288/MAX1289. Code transitions

occur halfway between successive-integer LSB values.

Applications Information

Automatic Shutdown Mode

With CNVST low, the MAX1286–MAX1289 default to an

AutoShutdown state (< 0.2µA) after power-up and

between conversions. After detecting a rising edge on

CNVST, the part powers up, sets DOUT low, and enters

track mode. After detecting a falling edge on CNVST, the

device enters hold mode and begins the conversion. A

maximum of 3.7µs later, the device completes conver-

sion, enters shutdown, and MSB is available at DOUT.

External Reference

An external reference is required for the MAX1286–

MAX1289. Use a 0.1µF bypass capacitor for best per-

formance. The reference input structure allows a volt-

age range of +1V to V

+ 50mV.

Connection to Standard Interfaces

The MAX1286–MAX1289 feature a serial interface that is

fully compatible with SPI, QSPI, and MICROWIRE. If a

serial interface is available, establish the CPU’s serial

interface as a master, so that the CPU generates the seri-

al clock for the ADCs. Select a clock frequency up to

8MHz.

How to Perform a Conversion

1) Use a general-purpose I/O line on the CPU to hold

CNVST low between conversions.

2) Drive CNVST high to acquire AIN1(MAX1286/

MAX1287) or unipolar mode (MAX1288/MAX1289).

To acquire AIN2 (MAX1286/MAX1287) or bipolar

mode (MAX1288/MAX1289), drive CNVST low and

high again.

3) Hold CNVST high for 1.4µs.

4) Drive CNVST low and wait approximately 3.7µs for

conversion to complete. After 3.7µs, the MSB is

available at DOUT.

OUTPUT CODE

FULL-SCALE

TRANSITION

11 . . . 111

11 . . . 110

11 . . . 101

00 . . . 011

00 . . . 010

00 . . . 001

00 . . . 000

123

FS - 3/2 LSB

FS = V

REF

ZS = GND

INPUT VOLTAGE (LSB)

MAX1286–

MAX1289

1 LSB =

REF

4096

Figure 6. Unipolar Transfer Function

011 . . . 111

011 . . . 110

000 . . . 010

000 . . . 001

000 . . . 000

111 . . . 111

111 . . . 110

111 . . . 101

100 . . . 001

100 . . . 000

- FS

INPUT VOLTAGE (LSB)

OUTPUT CODE

ZS = 0

+FS - 1 LSB

COM

REF

/ 2 *V

= (AIN+) - (AIN-)

REF

-FS =

-V

REF

≤

MAX1288/MAX1289

1 LSB =

REF

4096

Figure 7. Bipolar Transfer Function

5) Activate SCLK for a minimum of 12 rising clock

edges. DOUT transitions on SCLK’s falling edge

and is available in MSB-first format. Observe the

SCLK to DOUT valid timing characteristic. Clock

data into the µP on SCLK’s rising edge.

SPI and MICROWIRE Interface

When using an SPI (Figure 8a) or MICROWIRE inter-

face (Figures 8a and 8b), set CPOL = CPHA = 0. Two

8-bit readings are necessary to obtain the entire 12-bit

result from the ADC. DOUT data transitions on the seri-

al clock’s falling edge and is clocked into the µP on

SCLK’s rising edge. The first 8-bit data stream contains

the first 8-bits of DOUT starting with the MSB. The sec-

ond 8-bit data stream contains the remaining four result

bits. DOUT then goes high impedance.

QSPI Interface

Using the high-speed QSPI interface (Figure 9a) with

CPOL = 0 and CPHA = 0, the MAX1286–MAX1289

support a maximum f

SCLK

of 8MHz. One 12- to 16-bit

reading is necessary to obtain the entire 12-bit result

from the ADC. DOUT data transitions on the serial

clock’s falling edge and is clocked into the µP on

SCLK’s rising edge. The first 12 bits are the data.

DOUT then goes high impedance (Figure 9b).

PIC16 and SSP Module and

PIC17 Interface

The MAX1286–MAX1289 are compatible with a

PIC16/PIC17 µC, using the synchronous serial port

(SSP) module

To establish SPI communication, connect the controller

as shown in Figure 10a and configure the PIC16/PIC17

as system master. This is done by initializing its syn-

chronous serial port control register (SSPCON) and

synchronous serial port status register (SSPSTAT) to

the bit patterns shown in Tables 1 and 2.

In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data

to be synchronously transmitted and received simulta-

neously. Two consecutive 8-bit readings (Figure 10b)

are necessary to obtain the entire 12-bit result from the

ADC. DOUT data transitions on the serial clock’s falling

edge and is clocked into the µC on SCLK’s rising edge.

The first 8-bit data stream contains the first 8 data bits

starting with the MSB. The second data stream con-

tains the remaining bits, D3 through D0.

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

______________________________________________________________________________________ 11

Figure 8a. SPI Connections Figure 8b. MICROWIRE Connections

CNVST

SCLK

DOUT

I/O

SCK

MISO

SPI

MAX1286–

MAX1289

MAX1286–

MAX1289

CNVST

SCLK

DOUT

I/O

MICROWIRE

Table 1. Detailed SSPCON Register Content

CONTROL BIT

MAX1286–MAX1289

SETTINGS

SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON)

WCOL Bit 7 X Write Collision Detection Bit

SSPOV Bit 6 X Receive Overflow Detect Bit

SSPEN Bit 5 1

Synchronous Serial Port Enable Bit:

0: Disables serial port and configures these pins as I/O port pins.

1: E nab l es ser i al p or t and confi g ur es S C K, S D O, and S C I p i ns as ser i al p or t p i ns.

CKP Bit 4 0 Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.

SSPM3 Bit 3 0

SSPM2 Bit 2 0

SSPM1 Bit 1 0

SSPM0 Bit 0 1

Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects

CLK

= f

OSC

/ 16.

MAX1286–MAX1289

Layout, Grounding, and Bypassing

For best performance, use printed circuit (PC) boards.

Wire-wrap configurations are not recommended since

the layout should ensure proper separation of analog

and digital traces. Do not run analog and digital lines

parallel to each other, and do not lay out digital signal

paths underneath the ADC package. Use separate

analog and digital PC board ground sections with only

one starpoint (Figure 11), connecting the two ground

systems (analog and digital). For lowest-noise opera-

tion, ensure the ground return to the star ground’s

power supply is low impedance and as short as possi-

ble. Route digital signals far away from sensitive analog

and reference inputs.

High-frequency noise in the power supply (V

) may

degrade the performance of the ADC’s fast comparator.

Bypass V

to the star ground with a 0.1µF capacitor,

located as close as possible to the MAX1286–MAX1289s’

power-supply pin. Minimize capacitor lead length for best

supply-noise rejection. Add an attenuation resistor (5Ω) if

the power supply is extremely noisy.

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

12 ______________________________________________________________________________________

CNVST

SCLK

DOUT

SCK

MISO

QSPI

MAX1286–

MAX1289

Figure 9a. QSPI Connections

Table 2. Detailed SSPSTAT Register Content

CONTROL BIT

MAX1286–MAX1289

SETTINGS

SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT)

SMP Bit 7 0

SPI Data Input Sample Phase. Input data is sampled at the middle of the data

output time.

CKE Bit 6 1

SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial

clock.

D/A Bit 5 X Data Address Bit

P Bit 4 X Stop Bit

S Bit 3 X Start Bit

R/W Bit 2 X Read/Write Bit Information

UA Bit 1 X Update Address

BF Bit 0 X Buffer Full Status Bit

Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)

CNVST

1ST BYTE READ

SCLK

DOUT

2ND BYTE READ

SAMPLING INSTANT

418

B11

MSB

B10 B9 B8 B7

B5 B4 B3 B2 B1

LSB

HIGH-Z

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

MAX1288ETA+T

Mfr. #:

Buy MAX1288ETA+T

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC Ic Adc 12Bit 150ksps 5.25V Precision ADC

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