PDF: 09005aef80a8e793/Source: 09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.
dd5c16_32x72h.fm - Rev. F 2/07 EN
9 ©2004 Micron Technology, Inc. All rights reserved.
128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
Electrical Specifications
IDD Specifications
Tabl e 9: DDR IDD Specifications and Conditions – 128MB
Values shown for MT46V16M16 DDR SDRAM only and are computed from values specified in the
256Mb (16 Meg x 16) component data sheet
Parameter/Condition Symbol -335 -262
-26A/
-265 Units
Operating one bank active-precharge current:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once
per clock cycle; Address and control inputs changing once every two clock
cycles
IDD0 625 625 525 mA
Operating one bank active-read-precharge current: Burst = 4;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN);
I
OUT = 0mA; Address and control inputs changing once per clock cycle
IDD1 900 850 775 mA
Precharge power-down standby current: All device banks idle; Power-
down mode;
t
CK =
t
CK (MIN); CKE = (LOW)
IDD2P 20 20 20 mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN);
CKE = HIGH; Address and other control inputs changing once per clock
cycle; V
IN = VREF for DQ, DQS, and DM
IDD2F 250 225 225 mA
Active power-down standby current: One device bank active; Power-
down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD3P 150 125 125 mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank;
Active-precharge;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
IDD3N 300 250 250 mA
Operating current: Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); IOUT = 0mA
IDD4R 1,100 925 925 mA
Operating current: Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
IDD4W 900 725 725 mA
Auto refresh current
t
REFC =
t
RFC (MIN)
IDD5 1,275 1,175 1,175 mA
t
REFC = 7.8125µs
IDD5A 30 30 30 mA
Self refresh current: CKE ≤ 0.2V
IDD6202020mA
Operating current: Four device bank interleaving READs (BL = 4) with
auto precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address and control
inputs change only during active READ or WRITE commands
IDD7 2,200 1,900 1,900 mA
