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SST25VF010A-33-4C-SAE-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
©2011 Silicon Storage Technology, Inc. S725081A 10/11
13
1 Mbit SPI Serial Flash
SST25VF010A
Data Sheet
A
Microchip Technology Company
Auto Address Increment (AAI) Program
The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the
next sequential address location. This feature decreases total programming time when the entire mem-
ory array is to be programmed. An AAI program instruction pointing to a protected memory area will be
ignored. The selected address range must be in the erased state (FFH) when initiating an AAI program
instruction.
Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI program
instruction is initiated by executing an 8-bit command, AFH, followed by address bits [A
23
-A
0
]. Follow-
ing the addresses, the data is input sequentially from MSB (bit 7) to LSB (bit 0). CE# must be driven
high before the AAI program instruction is executed. The user must poll the BUSY bit in the software
status register or wait T
BP
for the completion of each internal self-timed Byte-Program cycle. Once the
device completes programming byte, the next sequential address may be program, enter the 8-bit
command, AFH, followed by the data to be programmed. When the last desired byte had been pro-
grammed, execute the Write-Disable (WRDI) instruction, 04H, to terminate AAI. After execution of the
WRDI command, the user must poll the Status register to ensure the device completes programming.
See Figure 7 for AAI programming sequence.
There is no wrap mode during AAI programming; once the highest unprotected memory address is
reached, the device will exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0).
Figure 7: Auto Address Increment (AAI) Program Sequence
CE#
SI
SCK
A[23:16] A[15:8] A[7:0]
AF
Data Byte 1
AF
DataByte2
CE#
SI
SO
SCK
Write Disable (WRDI)
Instruction to terminate
AAI Operation
Read Status Register (RDSR)
Instruction to verify end of
AAI Operation
04Last Data ByteAF
05
D
OUT
MODE 3
MODE 0
T
BP
T
BP
T
BP
1265 F07.0
012345678 323334353637383915 16 23 24 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 01
012345670123456789101112131415 0123456789101112131415
©2011 Silicon Storage Technology, Inc. S725081A 10/11
14
1 Mbit SPI Serial Flash
SST25VF010A
Data Sheet
A
Microchip Technology Company
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-
Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the any
command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, fol-
lowed by address bits [A
23
-A
0
]. Address bits [A
MS
-A
12
](A
MS
= Most Significant address) are used to
determine the sector address (SA
X
), remaining address bits can be V
IL
or V
IH.
CE# must be driven high
before the instruction is executed. The user may poll the Busy bit in the software status register or wait
T
SE
for the completion of the internal self-timed Sector-Erase cycle. See Figure 8 for the Sector-Erase
sequence.
Figure 8: Sector-Erase Sequence
Block-Erase
The Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-
Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any com-
mand sequence. The Block-Erase instruction is initiated by executing an 8-bit command, 52H or D8H,
followed by address bits [A
23
-A
0
]. Address bits [A
MS
-A
15
](A
MS
= Most significant address) are used to
determine block address (BA
X
), remaining address bits can be V
IL
or V
IH
. CE# must be driven high before
the instruction is executed. The user may poll the Busy bit in the software status register or wait T
BE
for the
completion of the internal self-timed Block-Erase cycle. See Figure 9 for the Block-Erase sequence.
Figure 9: Block-Erase Sequence
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.
20
HIGH IMPEDANCE
15 16
23
24
31
MODE 0
MODE 3
1265 F08.0
MSBMSB
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.
52 or D8
HIGH IMPEDANCE
15 16
23
24
31
MODE 0
MODE 3
1265 F09.0
MSB MSB
©2011 Silicon Storage Technology, Inc. S725081A 10/11
15
1 Mbit SPI Serial Flash
SST25VF010A
Data Sheet
A
Microchip Technology Company
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored
if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence.
The Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven
high before the instruction is executed. The user may poll the Busy bit in the software status register or wait
T
CE
for the completion of the internal self-timed Chip-Erase cycle. See Figure 10 for the Chip-Erase
sequence.
Figure 10:Chip-Erase Sequence
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register
may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in
progress, the Busy bit may be checked before sending any new commands to assure that the new
commands are properly received by the device. CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing
clock cycles until it is terminated by a low to high transition of the CE#. See Figure 11 for the RDSR
instruction sequence.
Figure 11:Read-Status-Register (RDSR) Sequence
CE#
SO
SI
SCK
01234567
60 or C7
HIGH IMPEDANCE
MODE 0
MODE 3
1265 F10.0
MSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
1265 F11.0
MODE 3
SCK
SI
SO
CE#
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
05
MODE 0
HIGH IMPEDANCE
Status
Register Out
MSB
MSB
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SST25VF010A-33-4C-SAE-T

Mfr. #:
Buy SST25VF010A-33-4C-SAE-T
Manufacturer:
Microchip Technology
Description:
NOR Flash 1M (128Kx8) 33MHz 2.7-3.6V Commercial
Lifecycle:
New from this manufacturer.
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