©2011 Silicon Storage Technology, Inc. S725081A 10/11
16
1 Mbit SPI Serial Flash
SST25VF010A
Data Sheet
A
Microchip Technology Company
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-Enable-Latch bit to 1 allowing Write operations to
occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE#
must be driven high before the WREN instruction is executed.
Figure 12:Write Enable (WREN) Sequence
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit and AAI bit to 0 disabling any
new Write operations from occurring. CE# must be driven high before the WRDI instruction is exe-
cuted.
Figure 13:Write Disable (WRDI) Sequence
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR)
instruction and opens the status register for alteration. The Enable-Write-Status-Register instruction
does not have any effect and will be wasted, if it is not followed immediately by the Write-Status-Regis-
ter (WRSR) instruction. CE# must be driven low before the EWSR instruction is entered and must be
driven high before the EWSR instruction is executed.
CE#
SO
SI
SCK
01234567
06
HIGH IMPEDANCE
MODE 0
MODE 3
1265 F12.0
MSB
CE#
SO
SI
SCK
01234567
04
HIGH IMPEDANCE
MODE 0
MODE 3
1265 F13.0
MSB
©2011 Silicon Storage Technology, Inc. S725081A 10/11
17
1 Mbit SPI Serial Flash
SST25VF010A
Data Sheet
A
Microchip Technology Company
Write-Status-Register (WRSR)
The Write-Status-Register instruction works in conjunction with the Enable-Write-Status-Register
(EWSR) instruction to write new values to the BP1, BP0, and BPL bits of the status register. The Write-
Status-Register instruction must be executed immediately after the execution of the Enable-Write-Sta-
tus-Register instruction (very next instruction bus cycle). This two-step instruction sequence of the
EWSR instruction followed by the WRSR instruction works like SDP (software data protection) com-
mand structure which prevents any accidental alteration of the status register values. The Write-Sta-
tus-Register instruction will be ignored when WP# is low and BPL bit is set to “1”. When the WP# is
low, the BPL bit can only be set from “0” to “1” to lock-down the status register, but cannot be reset
from “1” to “0”. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0,
and BP1 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP# pin is
driven high (V
IH
) prior to the low-to-high transition of the CE# pin at the end of the WRSR instruction,
the BP0, BP1, and BPL bit in the status register can all be altered by the WRSR instruction. In this
case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as
altering the BP0 and BP1 bit at the same time. See Table 3 for a summary description of WP# and BPL
functions. CE# must be driven low before the command sequence of the WRSR instruction is entered
and driven high before the WRSR instruction is executed. See Figure 14 for EWSR and WRSR instruc-
tion sequences.
Figure 14:Enable-Write-Status-Register (EWSR) and Write-Status-Register (WRSR)
Sequence
1265 F14.0
MODE 3
HIGH IMPEDANCE
MODE 0
STATUS
REGISTER IN
76543210
MSBMSBMSB
01
MODE 3
SCK
SI
SO
CE#
MODE 0
50
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
©2011 Silicon Storage Technology, Inc. S725081A 10/11
18
1 Mbit SPI Serial Flash
SST25VF010A
Data Sheet
A
Microchip Technology Company
Read-ID
The Read-ID instruction identifies the device as SST25VF010A and manufacturer as SST. The device
information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A
23
-
A
0
]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the
device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer’s and
device ID output data toggles between address 00000H and 00001H until terminated by a low to high
transition on CE#.
Figure 15:Read-ID Sequence
1265 F15.0
CE#
SO
SI
SCK
00
012345678
00 ADD
1
90 or AB
HIGH IMPEDANCE
15 16
23
24
31
32
39
40
47 48 55 56 63
BF
Device ID
BF
Device ID
Note: The manufacturer s and device ID output stream is continuous until terminated by a low to high transition on CE#.
1. 00H will output the manfacturer s ID first and 01H will output device ID first before toggling between the two.
HIGH
IMPEDANCE
MODE 3
MODE 0
MSB MSB
MSB

SST25VF010A-33-4C-SAE-T

Mfr. #:
Manufacturer:
Microchip Technology
Description:
NOR Flash 1M (128Kx8) 33MHz 2.7-3.6V Commercial
Lifecycle:
New from this manufacturer.
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