SST25PF080B
DS20005137B-page 10 2014 Microchip Technology Inc.
bit command, 70H, must be executed prior to initiating
an AAI Word-Program instruction. Once an internal
programming operation begins, asserting CE# will
immediately drive the status of the internal flash status
on the SO pin. A ‘0’ indicates the device is busy and a
‘1’ indicates the device is ready for the next instruction.
De-asserting CE# will return the SO pin to tri-state.
While in AAI and Hardware End-of-Write detection
mode, the only valid instructions are AAI Word (ADH)
and WRDI (04H).
To exit AAI Hardware End-of-Write detection, first exe-
cute WRDI instruction, 04H, to reset the Write-Enable-
Latch bit (WEL=0) and AAI bit. Then execute the 8-bit
DBSY command, 80H, to disable RY/BY# status during
the AAI command. See Figures 4-7 and 4-8.
FIGURE 4-6: ENABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
FIGURE 4-7: DISABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
CE#
SO
SI
SCK
01234567
70
HIGH IMPEDANCE
MODE 0
MODE 3
25137 EnableSO.0
MSB
CE#
SO
SI
SCK
01234567
80
HIGH IMPEDANCE
MODE 0
MODE 3
25137 DisableSO.0
MSB
2014 Microchip Technology Inc. DS20005137B-page 11
SST25PF080B
FIGURE 4-8: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
HARDWARE END-OF-WRITE DETECTION
FIGURE 4-9: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
SOFTWARE END-OF-WRITE DETECTION
CE#
SI
SCK
SO
25137 AAI.HW.3
Check for Flash Busy Status to load next valid
1
command
Load AAI command, Address, 2 bytes data
Note: 1. Valid commands during AAI programming: AAI command or WRDI command
2. User must configure the SO pin to output Flash Busy status during AAI programming
0
AAA
AD
D0 AD
MODE 3
MODE 0
D1 D2 D3
7
WREN
EBSY
0
7
078 32 4715 16 23 24 31 04039 7 8 15 16 23
D
OUT
WRDI followed by DBSY
to exit AAI Mode
WRDI RDSR
7015780
DBSY
70
CE# cont.
SI cont.
SCK cont.
SO cont.
Last 2
Data Bytes
AD
D
n-1
D
n
7 8 15 16 230
Check for Flash Busy Status to load next valid
1
command
078 32 4715 16 23 24 31 04039 7 8 15 16 23 7 8 15 16 23 70 157800
CE#
SI
SCK
SO
D
OUT
MODE 3
MODE 0
25137 AAI.SW.3
Note: 1. Valid commands during AAI programming: AAI command, RDSR command, or WRDI command
Wait T
BP
or poll Software Status
register to load next valid
1
command
Last 2
Data Bytes
WRDI to exit
AAI Mode
Load AAI command, Address, 2 bytes data
AAAAD D0 ADD1 D2 D3 AD
D
n-1
D
n
WRDI
RDSR
SST25PF080B
DS20005137B-page 12 2014 Microchip Technology Inc.
4.5.7 4-KBYTE SECTOR-ERASE
The Sector-Erase instruction clears all bits in the
selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must
remain active low for the duration of any command
sequence. The Sector-Erase instruction is initiated by
executing an 8-bit command, 20H, followed by address
bits [A
23
-A
0
]. Address bits [A
MS
-A
12
] (A
MS
= Most Sig-
nificant address) are used to determine the sector
address (SA
X
), remaining address bits can be V
IL
or V
IH.
CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software
status register or wait T
SE
for the completion of the
internal self-timed Sector-Erase cycle. See Figure 4-10
for the Sector-Erase sequence.
FIGURE 4-10: SECTOR-ERASE SEQUENCE
4.5.8 32-KBYTE AND 64-KBYTE BLOCK-
ERASE
The 32-KByte Block-Erase instruction clears all bits in
the selected 32 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. The 64-KByte Block-Erase instruction clears all bits
in the selected 64 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must remain
active low for the duration of any command sequence.
The 32-KByte Block-Erase instruction is initiated by
executing an 8-bit command, 52H, followed by address
bits [A
23
-A
0
]. Address bits [A
MS
-A
15
] (A
MS
= Most Sig-
nificant Address) are used to determine block address
(BA
X
), remaining address bits can be V
IL
or V
IH.
CE#
must be driven high before the instruction is executed. The
64-KByte Block-Erase instruction is initiated by executing an
8-bit command D8H, followed by address bits [A
23
-A
0
].
Address bits [A
MS
-A
16
] are used to determine block address
(BA
X
), remaining address bits can be V
IL
or V
IH.
CE# must
be driven high before the instruction is executed. The user
may poll the Busy bit in the software status register or wait
T
BE
for the completion of the internal self-timed 32-
KByte Block-Erase or 64-KByte Block-Erase cycles.
See Figures 4-11 and 4-12 for the 32-KByte Block-
Erase and 64-KByte Block-Erase sequences.
FIGURE 4-11: 32-KBYTE BLOCK-ERASE SEQUENCE
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.
20
HIGH IMPEDANCE
15 16
23
24
31
MODE 0
MODE 3
25137 SecErase.0
MSBMSB
CE#
SO
SI
SCK
ADDR
012345678
ADDR ADDR
52
HIGH IMPEDANCE
15 16
23
24
31
MODE 0
MODE 3
25137 32KBklEr.0
MSB MSB

SST25PF080B-80-4C-QAE

Mfr. #:
Manufacturer:
Microchip Technology
Description:
NOR Flash 2.3V to 3.6V 8Mbit SPI Serial Flash
Lifecycle:
New from this manufacturer.
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