SST25PF080B
DS20005137B-page 12 2014 Microchip Technology Inc.
4.5.7 4-KBYTE SECTOR-ERASE
The Sector-Erase instruction clears all bits in the
selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must
remain active low for the duration of any command
sequence. The Sector-Erase instruction is initiated by
executing an 8-bit command, 20H, followed by address
bits [A
23
-A
0
]. Address bits [A
MS
-A
12
] (A
MS
= Most Sig-
nificant address) are used to determine the sector
address (SA
X
), remaining address bits can be V
IL
or V
IH.
CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software
status register or wait T
SE
for the completion of the
internal self-timed Sector-Erase cycle. See Figure 4-10
for the Sector-Erase sequence.
FIGURE 4-10: SECTOR-ERASE SEQUENCE
4.5.8 32-KBYTE AND 64-KBYTE BLOCK-
ERASE
The 32-KByte Block-Erase instruction clears all bits in
the selected 32 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. The 64-KByte Block-Erase instruction clears all bits
in the selected 64 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must remain
active low for the duration of any command sequence.
The 32-KByte Block-Erase instruction is initiated by
executing an 8-bit command, 52H, followed by address
bits [A
23
-A
0
]. Address bits [A
MS
-A
15
] (A
MS
= Most Sig-
nificant Address) are used to determine block address
(BA
X
), remaining address bits can be V
IL
or V
IH.
CE#
must be driven high before the instruction is executed. The
64-KByte Block-Erase instruction is initiated by executing an
8-bit command D8H, followed by address bits [A
23
-A
0
].
Address bits [A
MS
-A
16
] are used to determine block address
(BA
X
), remaining address bits can be V
IL
or V
IH.
CE# must
be driven high before the instruction is executed. The user
may poll the Busy bit in the software status register or wait
T
BE
for the completion of the internal self-timed 32-
KByte Block-Erase or 64-KByte Block-Erase cycles.
See Figures 4-11 and 4-12 for the 32-KByte Block-
Erase and 64-KByte Block-Erase sequences.
FIGURE 4-11: 32-KBYTE BLOCK-ERASE SEQUENCE
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.
20
HIGH IMPEDANCE
15 16
23
24
31
MODE 0
MODE 3
25137 SecErase.0
MSBMSB
CE#
SO
SI
SCK
ADDR
012345678
ADDR ADDR
52
HIGH IMPEDANCE
15 16
23
24
31
MODE 0
MODE 3
25137 32KBklEr.0
MSB MSB