SST25PF080B
DS20005137B-page 22 2014 Microchip Technology Inc.
FIGURE 5-2: SERIAL OUTPUT TIMING DIAGRAM
FIGURE 5-3: HOLD TIMING DIAGRAM
25137 SerOut.0
CE#
SI
SO
SCK
MSB
T
CLZ
T
V
T
SCKH
T
CHZ
T
OH
T
SCKL
LSB
T
HZ
T
LZ
T
HHH
T
HLS
T
HHS
25137 Hold.0
HOLD#
CE#
SCK
SO
SI
T
HLH
2014 Microchip Technology Inc. DS20005137B-page 23
SST25PF080B
5.1 Power-Up Specifications
All functionalities and DC specifications are specified
for a V
DD
ramp rate of greater than 1V per 100 ms (0V
- 3.0V in less than 300 ms). See Table 5-8 and Figure
5-4 for more information.
FIGURE 5-4: POWER-UP TIMING DIAGRAM
TABLE 5-8: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol Parameter Minimum Units
T
PU-READ
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
V
DD
Min to Read Operation 100 µs
T
PU-WRITE
1
V
DD
Min to Write Operation 100 µs
Time
V
DD
Min
V
DD
Max
V
DD
Device fully accessible
T
PU-READ
T
PU-WRITE
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.
25137 PwrUp.0
SST25PF080B
DS20005137B-page 24 2014 Microchip Technology Inc.
FIGURE 5-5: AC INPUT/OUTPUT REFERENCE WAVEFORMS
FIGURE 5-6: A TEST LOAD EXAMPLE
25137 IORef.0
REFERENCE POINTS OUTPUTINPUT
V
HT
V
LT
V
HT
V
LT
V
IHT
V
ILT
AC test inputs are driven at V
IHT
(0.9V
DD
) for a logic “1” and V
ILT
(0.1V
DD
) for a logic “0”. Measurement
reference points for inputs and outputs are V
HT
(0.6V
DD
) and V
LT
(0.4V
DD
). Input rise and fall times (10%
90%) are <5 ns.
Note: V
HT
- V
HIGH
Test
V
LT
- V
LOW
Test
V
IHT
- V
INPUT
HIGH Test
V
ILT
- V
INPUT
LOW Test
25137 TstLd.0
TO TESTER
TO DUT
C
L

SST25PF080B-80-4C-QAE

Mfr. #:
Manufacturer:
Microchip Technology
Description:
NOR Flash 2.3V to 3.6V 8Mbit SPI Serial Flash
Lifecycle:
New from this manufacturer.
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