DS017 (v2.4) September 15, 2008 www.xilinx.com 1
Product Specification
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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• Low power 3.3V 64 macrocell CPLD
• 5.5 ns pin-to-pin logic delays
• System frequencies up to 192 MHz
• 64 macrocells with 1,500 usable gates
• Available in small footprint packages
- 44-pin VQFP (36 user I/O pins)
- 48-ball CS BGA (40 user I/O pins)
- 56-ball CP BGA (48 user I/O pins)
- 100-pin VQFP (68 user I/O pins)
• Optimized for 3.3V systems
- Ultra-low power operation
- Typical Standby Current of 17 μA at 25°C
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power CMOS design technology
- 3.3V PCI electrical specification compatible
outputs (no internal clamp diode on any input or
I/O, no minimum clock input capacitance)
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
• Fast ISP programming times
• Port Enable pin for dual function of JTAG ISP pins
• 2.7V to 3.6V supply voltage at industrial temperature
range
• Programmable slew rate control per macrocell
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012
) for
architecture description
Description
The CoolRunner™ XPLA3 XCR3064XL device is a 3.3V,
64-macrocell CPLD targeted at power sensitive designs
that require leading edge programmable logic solutions. A
total of four function blocks provide 1,500 usable gates.
Pin-to-pin propagation delays are as fast as 5.5 ns with a
maximum system frequency of 192 MHz.
TotalCMOS Design Technique for Fast
Zero Power
CoolRunner XPLA3 CPLDs offer a TotalCMOS solution,
both in process technology and design technique. Xilinx
employs a cascade of CMOS gates to implement its sum of
products instead of the traditional sense amp approach.
This CMOS gate implementation allows Xilinx to offer
CPLDs that are both high performance and low power,
breaking the paradigm that to have low power, you must
have low performance. Refer to Figure 1 and Table 1 show-
ing the I
CC
vs. Frequency of our XCR3064XL TotalCMOS
CPLD (data taken with four resetable up/down, 16-bit
counters at 3.3V, 25° C).
0
XCR3064XL 64 Macrocell CPLD
DS017 (v2.4) September 15, 2008
014
Product Specification
Figure 1: I
CC
vs. Frequency at V
CC
= 3.3V, 25°C
1
1
2
2
4
4
2
4
6
8
1
12
18
14
16
Frequenc
(MHz)
S017
01
06250
pical
mA
Tabl e 1: I
CC
vs. Frequency (V
CC
= 3.3V, 25°C)
Frequency
(MHz) 0 1 5 10 20 40 60 80 100 120 140 160 180
Typical I
CC
(mA) 0.017 0.24 1.09 2.15 4.28 8.50 12.85 16.80 20.80 25.72 29.89 33.53 36.27
