XCR3064XL-10VQG100I

XCR3064XL 64 Macrocell CPLD
4 www.xilinx.com DS017 (v2.4) September 15, 2008
Product Specification
R
Internal Timing Parameters
Symbol Parameter
(1, 2)
-6 -7 -10
UnitMin. Max. Min. Max. Min. Max.
Buffer Delays
T
IN
Input buffer delay - 1.3 - 1.6 - 2.2 ns
T
FIN
Fast Input buffer delay - 2.3 - 3.0 - 3.1 ns
T
GCK
Global Clock buffer delay - 0.8 - 1.0 - 1.3 ns
T
OUT
Output buffer delay - 2.2 - 2.7 - 3.6 ns
T
EN
Output buffer enable/disable delay - 4.2 - 5.0 - 5.7 ns
Internal Register and Combinatorial Delays
T
LDI
Latch transparent delay - 1.3 - 1.6 - 2.0
T
SUI
Register setup time 1.0 - 1.0 - 1.2 - ns
T
HI
Register hold time 0.3 - 0.5 - 0.7 - ns
T
ECSU
Register clock enable setup time 2.0 - 2.5 - 3.0 - ns
T
ECHO
Register clock enable hold time 3.0 - 4.5 - 5.5 - ns
T
COI
Register clock to output delay - 1.0 - 1.3 - 1.6 ns
T
AOI
Register async. S/R to output delay - 2.5 - 2.3 - 2.1 ns
T
RAI
Register async. recovery - 4.0 - 5.0 - 6.0 ns
T
PTCK
Product term clock delay - 2.5 - 2.7 - 3.3 ns
T
LOGI1
Internal logic delay (single p-term) - 2.0 - 2.7 - 3.3 ns
T
LOGI2
Internal logic delay (PLA OR term) - 2.5 - 3.2 - 4.2 ns
Feedback Delays
T
F
ZIA delay - 0.7 - 2.9 - 3.5 ns
Time Adders
T
LOGI3
Fold-back NAND delay - 2.0 - 2.5 - 3.0 ns
T
UDA
Universal delay - 1.5 - 2.0 - 2.5 ns
T
SLEW
Slew rate limited delay - 4.0 - 5.0 - 6.0 ns
Notes:
1. These parameters guaranteed by design and/or characterization, not testing.
2. See the CoolRunner XPLA3 family data sheet (
DS012) for timing model.
XCR3064XL 64 Macrocell CPLD
DS017 (v2.4) September 15, 2008 www.xilinx.com 5
Product Specification
R
Switching Characteristics
Figure 3: AC Load Circuit
DS017_03_102401
Component Values
R1 390Ω
R2 390Ω
C1 35 pF
Measurement S1 S2
T
POE
(High)
T
POE
(Low)
T
P
Open Closed
Closed Open
Closed
Closed
V
CC
V
OUT
V
IN
C1
R1
R2
S1
S2
Note: For T
POD
, C1 = 5 pF. Delay measured at
output level of V
OL
+ 300 mV, V
OH
– 300 mV.
Figure 4: Derating Curve for T
PD2
, 3.3V, 25°C
4.9
5.0
4.8
4.7
4.6
5.1
5.2
5.3
5.4
5.5
5.6
124816
DS017_04_062502
Number of Adjacent Outputs Switching
3.3V, 25°C
(ns)
Figure 5: Voltage Waveform
90%
10%
1.5 ns 1.5 ns
DS017_05_042800
+3.0V
0V
Measurements:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
T
R
T
L
XCR3064XL 64 Macrocell CPLD
6 www.xilinx.com DS017 (v2.4) September 15, 2008
Product Specification
R
Pin Descriptions
Tabl e 2: XCR3064XL User I/O Pins
PC44
(1)
VQ44 CS48 CP56 VQ100
Total User I/O
Pins
36 36 40 48 68
1. This is an obsolete package type. It remains here for legacy
support only
Tabl e 3: XCR3064XL I/O Pins
Function
Block
Macro-
cell
PC44
(1)
VQ44 CS48 CP56 VQ100
1 1 41 35 C5 C8 85
1 2 40 34 A6 A8 84
1 3----83
1 4---A981
1 5---A580
1 6 - - A7 A10 79
1 7----76
1 8 39 33 B6 B10 75
1938
(2)
32
(2)
B7
(2)
C10
(2)
73
(2)
1103731D4D871
1113630C6E869
1 12----68
1 13----67
1143428D6F865
1153327D7E1064
1 16----63
21442A2C492
22543A1C393
23644C4A194
2 4----96
2 5---B197
2 6----98
2 7---A299
2 8 - - B2 A3 100
297
(2)
1
(2)
B1
(2)
C1
(2)
4
(2)
21082C2D16
21193C1D38
2 12----9
2 13----10
214115D3E312
215126D1F113
2 16----14
3132
(2)
26
(2)
E5
(2)
F10
(2)
62
(2)
3 2 31 25 E7 G8 61
3 3----60
3 4 29 23 F7 H10 58
3 5----57
3 6----56
37--F6K854
3 8---K1052
3 9 28 22 G7 K9 48
3 10 27 21 G6 J10 47
3112620F5H846
3122519G5H745
3132418F4H644
3 14----42
3 15---K741
3 16----40
4113
(2)
7
(2)
D2
(2)
G1
(2)
15
(2)
42148E1F316
4 3----17
4 4 16 10 F1 G3 19
4 5 17 11 G1 J1 20
4 6----21
4 7----23
4 8---K125
4 9 18 12 E4 K4 29
4101913F2K230
4112014G2K331
4122115F3H332
413--G3H433
4 14----35
4 15---K536
4 16----37
Notes:
1. This is an obsolete package type. It remains here for legacy
support only.
2. JTAG pins.
Tabl e 3 : XCR3064XL I/O Pins
Function
Block
Macro-
cell
PC44
(1)
VQ44 CS48 CP56 VQ100

XCR3064XL-10VQG100I

Mfr. #:
Manufacturer:
Xilinx
Description:
CPLD - Complex Programmable Logic Devices XCR3064XL-10VQG100I
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union