Si8220/21
22 Rev. 1.2
9. Ordering Guide
Table 14. Si8220/21 Ordering Guide*
New Ordering
Part Number
(OPN)
Ordering Options
Input
Configuration
Peak Output
Current
(Cross Reference)
UVLO
Voltage
Insulation
Rating
Temp Range Pkg Type
Si8220BB-A-IS Opto input 2.5 A
(HCPL-3120)
8V
default
2.5 kVrms –40 to +125 °C SOIC-8
Si8220CB-A-IS Opto input 2.5 A
(HCPL-3120)
10 V 2.5 kVrms –40 to +125 °C SOIC-8
Si8220DB-A-IS Opto input 2.5 A
(HCPL-3120)
12.5 V 2.5 kVrms –40 to +125 °C SOIC-8
Si8220BD-A-IS Opto input 2.5 A
(HCPL-3120)
8V
default
5.0 kVrms –40 to +125 °C WB SOIC-16
Si8220CD-A-IS Opto input 2.5 A
(HCPL-3120)
10 V 5.0 kVrms –40 to +125 °C WB SOIC-16
Si8220DD-A-IS Opto input 2.5 A
(HCPL-3120)
12.5 V 5.0 kVrms –40 to +125 °C WB SOIC-16
Si8221CC-A-IS Opto input 0.5 A
(HCPL-0302)
10 V 3.75 kVrms –40 to +125 °C SOIC-8
Si8221DC-A-IS Opto input 0.5 A
(HCPL-0302)
12.5 V 3.75 kVrms –40 to +125 °C SOIC-8
*Note: All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard
classifications and peak solder temperatures.
Moisture sensitivity level is MSL2A for wide-body SOIC-16 packages.
Moisture sensitivity level is MSL2A for narrow-body SOIC-8 packages.
“Si” and “SI” are used interchangeably.
Si8220/21
Rev. 1.2 23
10. Package Outline: 8-Pin Narrow Body SOIC
Figure 18 illustrates the package details for the Si822x. Table 15 lists the values for the dimensions shown in the
illustration.
Figure 18. 8-pin Small Outline Integrated Circuit (SOIC) Package
Table 15. Package Diagram Dimensions
Symbol
Millimeters
Min Max
A 1.35 1.75
A1 0.10 0.25
A2 1.40 REF 1.55 REF
B 0.33 0.51
C 0.19 0.25
D 4.80 5.00
E 3.80 4.00
e 1.27 BSC
H 5.80 6.20
h 0.25 0.50
L 0.40 1.27
0 8
Si8220/21
24 Rev. 1.2
11. Land Pattern: 8-Pin Narrow Body SOIC
Figure 19 illustrates the recommended land pattern details for the Si822x in an 8-pin narrow-body SOIC. Table 16
lists the values for the dimensions shown in the illustration.
Figure 19. PCB Land Pattern: 8-Pin Narrow Body SOIC
Table 16. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC)
Dimension Feature (mm)
C1 Pad Column Spacing 5.40
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.

SI8220BD-D-ISR

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Gate Drivers 5 kV opto input isolated gate driver
Lifecycle:
New from this manufacturer.
Delivery:
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